Controlling atomic updates of indexes using hardware transactional memory

1. A system comprising:

at least one hardware device processor; and

a computer-readable storage medium storing executable instructions that, when executed, cause the at least one hardware device processor to:

control a page merge transformation of a current state of a mapping table to an updated state in a latch-free manner using a single hardware transaction in a hardware transactional memory, the single hardware transaction comprising at least one multi-word compare-and-swap operation that:

performs a first atomic step of the page merge transformation by marking a deleted page as deleted;

performs a second atomic step of the page merge transformation by merging an existing key of the deleted page to another page; and

performs a third atomic step of the page merge transformation by deleting an identifier of the deleted page from a parent page,

the mapping table being associated with a lock-free index of a database.

2. The system of claim 1 , wherein the third atomic step performed by the at least one multi-word compare-and-swap operation includes deleting at least one search key from the parent page.

3. The system of claim 1 , wherein the executable instructions, when executed, cause the at least one hardware device processor to:

bracket an entire index traversal in another single hardware transaction.

4. The system of claim 1 , wherein the at least one multi-word compare-and-swap operation consists of a single multi-word compare-and-swap operation.

5. The system of claim 1 , wherein the executable instructions, when executed, cause the at least one hardware device processor to:

perform one or more read operations non-transactionally.

6. The system of claim 1 , wherein the executable instructions, when executed, cause the at least one hardware device processor to:

bracket a plurality of multi-slot updates to the mapping table in other hardware transactions; and

perform singleton read operations and singleton write operations on the mapping table without using hardware transactions.

7. The system of claim 1 , wherein the executable instructions, when executed, cause the at least one hardware device processor to:

avoid one or more memory page faults by executing a fallback code path.

8. The system of claim 7 , wherein the fallback code path pre-faults particular addresses to be executed by one or more other hardware transactions.

9. The system of claim 8 , wherein the executable instructions, when executed, cause the at least one hardware device processor to:

retry executing the fallback code path for a configurable number of retries.

10. The system of claim 1 , wherein the executable instructions, when executed, cause the at least one hardware device processor to:

control another transformation by bracketing accesses to the mapping table in another single hardware transaction; and

provide another atomic multi-word compare-and-swap operation with exclusive access to target words via lockaside operations inside the another single hardware transaction.

11. The system of claim 10 , wherein the executable instructions, when executed, cause the at least one hardware device processor to:

maintain a respective thread-local read/write lock for each thread of a plurality of concurrently executing threads; and

before starting an operation by an individual thread, acquire exclusive access to an individual thread-local read/write lock for the individual thread,

wherein the lockaside operations include obtaining exclusive access to the mapping table by acquiring other respective thread-local read/write locks from other threads of the plurality of concurrently executing threads.

12. The system of claim 11 , wherein the executable instructions, when executed, cause the at least one hardware device processor to:

acquire the other respective thread-local read/write locks in a deterministic order.

13. The system of claim 12 , wherein the executable instructions, when executed, cause the at least one hardware device processor to:

modify target mapping table entries, by the individual thread, and release the other respective thread-local read/write locks after the target mapping table entries are modified.

14. A method performed via a device processor of a system having a hardware transactional memory, the method comprising:

controlling a page merge transformation of a first state of a mapping table to a second state of the mapping table, the controlling including initiating, within a single hardware transaction on the hardware transactional memory, at least one multi-word compare-and-swap operation, wherein:

the at least one multi-word compare-and-swap operation marks a deleted page as deleted;

the at least one multi-word compare-and-swap operation merges an existing key of the deleted page to another page; and

the at least one multi-word compare-and-swap operation deletes an identifier of the deleted page from a parent page.

15. The method of claim 14 , the at least one multi-word compare-and-swap operation consisting of a single multi-word compare-and-swap operation.

16. A computer program product comprising a computer-readable storage medium storing executable instructions that, when executed by at least one processor, cause the at least one processor to:

access a current state of one or more entries in a mapping table for a database index; and

using a single hardware transaction in a hardware transactional memory, transform the current state of the mapping table to a transformed state, the single hardware transaction comprising a page merge operation involving at least one multi-word compare-and-swap operation,

the at least one multi-word compare-and-swap operation marking a deleted page as deleted;

the at least one multi-word compare-and-swap operation merging an existing key of the deleted page to another page; and

the at least one multi-word compare-and-swap operation deleting an identifier of the deleted page from a parent page.

17. The computer program product of claim 16 , wherein the mapping table maps logical page identifiers to physical addresses.

18. The computer program product of claim 17 , wherein the physical addresses comprise memory addresses.

19. The computer program product of claim 17 , wherein the physical addresses comprise stable storage addresses.

20. The computer program product of claim 16 , the database index comprising a tree structure.