IP Library Granted Patent US 10,068,919
Granted Patent B2
US 10,068,919 · App. 14/714,352 · Granted Sep 4, 2018

Semiconductor device and method of forming the same

Inventor: Chin-Sheng Yang (Hsinchu, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L27/1207H01L21/845H01L27/0688H01L27/1225H01L21/8258H01L27/092H01L29/66545H01L29/66636H01L29/7842
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Quick Facts
Patent No.
US 10,068,919
App. No.
14/714,352
Granted
Sep 4, 2018
Kind
B2
Abstract

A semiconductor device and a method of forming the same, the semiconductor device includes a first transistor and a second transistor. The first transistor is disposed on a substrate and comprises a gate electrode, a gate dielectric layer and a first source/drain. The second transistor includes the gate electrode and a channel layer disposed on the gate electrode.

Claims (12)

1. A semiconductor device, comprising:

a first transistor disposed on a substrate, the first transistor comprising a gate electrode, a spacer surrounding the gate electrode, a gate dielectric layer, a first source/drain, and a first channel disposed in the substrate, below the gate electrode;

a second transistor, comprising the gate electrode, a dielectric layer, a channel layer covered on the gate electrode and the dielectric layer, a second source/drain disposed on the channel layer, and a portion of the channel layer acts as a second channel, the second channel remains integral to the channel layer and is disposed between the second source/drain, the first channel only partially overlapping the second channel and an extending direction of the first channel being in a first direction while another extending direction of the channel layer being in a second direction being perpendicular to the first direction, wherein the second channel comprises a different material from that of the first channel, and the spacer is simultaneously and directly in contact with the gate dielectric layer of the first transistor and the dielectric layer of the second transistor; and

a plurality of contact plugs disposed on the first transistor and the second transistor and are electrically connected thereto respectively, wherein a first contact plug of the plurality of contact plugs electrically connected to the first source/drain does not overlap a second contact plug of the plurality of contact plugs electrically connected to the second source/drain in a projection direction.

2. The semiconductor device of claim 1 , wherein the channel layer at least partially overlaps the gate electrode in a projecting direction being perpendicular to the substrate.

3. The semiconductor device of claim 1 , wherein the second source/drain comprises conductive layers disposed on two sides of the second channel.

4. The semiconductor device of claim 1 , wherein the first source/drain is disposed in the substrate.

5. The semiconductor device of claim 4 , wherein the first source/drain comprises an epitaxial structure.

6. The semiconductor device of claim 1 , wherein the first transistor and the second transistor comprises different conductive types.

7. The semiconductor device of claim 1 , wherein the channel layer comprises indium gallium zinc oxide (IGZO).

8. The semiconductor device of claim 1 , further comprising:

a fin shaped structure disposed in the substrate, and the first source/drain is disposed in the fin shaped structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 18, 2015
From: YANG, CHIN-SHENG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 035654/0585 →
Priority Claims (1)
CN 2015 1 0189060 · Apr 21, 2015 · national
Continuity (1)
Related Publication 20160315100A1 · Oct 27, 2016
Cited By (1)
US 12,684,848