Memristive neuromorphic circuit and method for training the memristive neuromorphic circuit

1. A method for training a memristive neuromorphic circuit, the method comprising:

providing a conductance balanced voltage pair that includes a set voltage and a reset voltage, wherein either one of the set voltage and the reset voltage, when applied to a memristive device that is connected to a neuron circuit, effects a substantially same magnitude conductance change in the memristive device over a predetermined range of conductance of the memristive device;

storing the provided voltage pair as a conductance balanced map; and

applying, based on the conductance balanced map, a training voltage to the memristive device.

2. The method of claim 1 , wherein

the step of providing includes

selecting the set voltage and the reset voltage, and

identifying an equilibrium region as the predetermined range of conductance of the memristive device by adjusting at least one of a duration of the set voltage, a duration of the reset voltage, an amplitude of the set voltage, and an amplitude of the reset voltage.

3. The method of claim 1 , further comprising:

based on the provided voltage pair, deriving a plurality of conductance balanced voltage pairs that effect different magnitude conductance changes from the provided voltage pair; and

storing the provided voltage pair and the plurality of derived voltage pairs as the conductance balanced map.

4. The method of claim 3 , wherein

the step of deriving includes extrapolating the plurality of derived voltage pairs from the provided voltage pair.

5. The method of claim 3 , wherein

the provided voltage pair includes a first conductance balanced voltage pair,

the step of providing includes providing a second conductance balanced voltage pair, and

the step of deriving includes interpolating the plurality of derived voltage pairs from the first voltage pair and the second voltage pair.

6. The method of claim 1 , wherein

the step of providing includes providing a plurality of conductance balanced voltage pairs, and

the step of storing includes storing the plurality of conductance balanced voltage pairs as the conductance balanced map.

7. The method of claim 1 , wherein

the provided voltage pair includes a masking voltage pair, and

the step of storing includes associating the masking voltage pair with an entire range of conductance of the memristive device.

8. The method of claim 1 , wherein

the conductance balanced maps stores the provided voltage pair in the form of:

V=f (Δ G )

for both the set voltage and the reset voltage, where V is one of the set voltage and the reset voltage, ΔG is the substantially same magnitude conductance change effected by the set voltage and the reset voltage, and f( ) is an arbitrary function.

9. The method of claim 1 , further comprising:

initializing the memristive device with an initial conductance such that when the training voltage is applied to the memristive device, the conductance of the memristive device is biased toward the predetermined range of conductance.

10. A memristive neuromorphic circuit, comprising:

a neuron circuit;

a memristive device that is connected to the neuron circuit; and

a controller including a processor and a memory, wherein

the memory is configured to store a conductance balanced map; and

the controller is configured to apply, based on the conductance balanced map, a training voltage to the memristive device, wherein

the conductance balanced map includes a conductance balanced voltage pair of a set voltage and a reset voltage, wherein either one of the set voltage and the reset voltage, when applied to the memristive device, effects a substantially same magnitude conductance change in the memristive device over a predetermined range of conductance of the memristive device.

11. The memristive neuromorphic circuit of claim 10 , further comprising:

a summing op-amp circuit connecting the neuron circuit to the memristive circuit, wherein

the summing op-amp circuit includes an adjustable feedback resistor value that scales a voltage signal transmitted from the neuron circuit to the memristive circuit.

12. The memristive neuromorphic circuit of claim 10 , wherein

the memristive device is a first memristive device of a differential pair of memristive devices connected to the neuron circuit, the differential pair of memristive devices including the first memristive device and a second memristive device.

13. The memristive neuromorphic circuit of claim 12 , further comprising:

a differential amplifier connected to the differential pair of memristive devices, the differential amplifier configured to calculate a difference between an output of the first memristive device and an output of the second memristive device.

14. The memristive neuromorphic circuit of claim 12 , wherein

the differential pair of memristive devices is a first differential pair of a plurality of differential pairs of memristive devices, and

the plurality of differential pairs of memristive devices are connected to the neuron circuit.

15. The memristive neuromorphic circuit of claim 10 , further including:

a plurality of crossbar nanowires, wherein

the neuron circuit, the memristive device, and the plurality of crossbar nanowires are connected together as a crossbar circuit.

16. The memristive neuromorphic circuit of claim 10 , wherein

the neuron circuit includes at least one of an input neuron and an output neuron.

17. The memristive neuromorphic circuit of claim 16 , wherein

the memristive device is connected between the input neuron and the output neuron.

18. The memristive neuromorphic circuit of claim 17 , further comprising:

a first summing op-amp circuit connected between the memristive device and the input neuron; and

a second summing op-amp circuit connected between the memristive device and the output neuron.

19. The memristive neuromorphic circuit of claim 18 , wherein

the input neuron, the first summing op-amp circuit, the memristive device, the second summing op-amp circuit, and the output neuron are integrally formed as a single integrated circuit.

20. A method for training a memristive neuromorphic circuit, the method comprising:

providing a first conductance balanced voltage pair that includes a first set voltage and a first reset voltage, wherein

the first set voltage, when applied to a memristive device that is connected to a neuron circuit, effects a first magnitude conductance change in the memristive device over a predetermined range of conductance of the memristive device, and

the first reset voltage, when applied to the memristive device, effects a second magnitude conductance change in the memristive device over the predetermined range of conductance of the memristive device;

providing a second conductance balanced voltage pair that includes a second set voltage and a second reset voltage, wherein

the second set voltage, when applied to the memristive device, effects a third magnitude conductance change in the memristive device over the predetermined range of conductance of the memristive device, and

the second reset voltage, when applied to the memristive device, effects a fourth magnitude conductance change in the memristive device over the predetermined range of conductance of the memristive device;

storing the provided first and second voltage pairs as a conductance balanced map; and

applying, based on the conductance balanced map, a training voltage to the memristive device, wherein

a ratio between the first magnitude and the second magnitude is substantially equal to a ratio between the third magnitude and the fourth magnitude.