IP Library › Granted Patent US 10,074,606

Granted Patent B2

US 10,074,606 · App. 15/464,487 · Granted Sep 11, 2018

Via, trench or contact structure in the metallization, prematallization dielectric or interlevel dielectric layers of an integrated circuit

Inventor: John Hongguang Zhang (Fishkill, NY)

Assignee: STMicroelectronics, Inc.

H01L23/528 H01L23/5226 H01L23/53228

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Quick Facts

Patent No.: US 10,074,606
App. No.: 15/464,487
Granted: Sep 11, 2018
Kind: B2

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USPTO Patent Center↗ Full Patent PDF↗

Abstract

A semiconductor substrate includes a doped region. A premetallization dielectric layer extends over the semiconductor substrate. A first metallization layer is disposed on a top surface of the premetallization dielectric layer. A metal contact extends from the first metallization layer to the doped region. The premetallization dielectric layer includes sub-layers, and the first metal contact is formed by sub-contacts, each sub-contact formed in one of the sub-layers. Each first sub-contact has a width and a length, wherein the lengths of the sub-contacts forming the metal contact are all different from each other.

Claims (52)

1. An integrated circuit, comprising:

a substrate; and

conductive interconnect structures over the substrate, said conductive interconnect structures including a first interconnect structure and a second interconnect structure; and

wherein:

the first interconnect structure is adjacent to the second interconnect structure;

the first interconnect structure includes a first substructure at a first level and a second substructure at a second level, the second level located at a greater distance from the substrate than the first level;

the second substructure of the first interconnect structure is electrically coupled to the first substructure of the first interconnect structure;

the second interconnect structure includes a first substructure at the first level and a second substructure at the second level;

the second substructure of the second interconnect structure is electrically coupled to the first substructure of the second interconnect structure;

the first substructure of the first interconnect structure has a length greater than a length of the first substructure of the second interconnect structure; and

the second substructure of the second interconnect structure having a length greater than a length of the second substructure of the first interconnect structure.

2. The circuit of claim 1 , wherein the second substructure of the first interconnect structure is electrically connected with the first substructure of the first interconnect structure.

3. The circuit of claim 1 , wherein the second substructure of the first interconnect structure is in physical contact with the first substructure of the first interconnect structure.

4. The circuit of claim 1 , wherein the second substructure of the second interconnect structure is electrically connected to the first substructure of the second interconnect structure.

5. The circuit of claim 1 , wherein the second substructure of the second interconnect structure is in physical contact with the first substructure of the second interconnect structure.

6. The circuit of claim 1 , wherein the second substructure of the first structure is in physical contact with the first substructure of the first interconnect structure, and wherein the second substructure of the second interconnect structure is in physical contact with the first substructure of the second interconnect structure.

7. The circuit of claim 1 , wherein a first distance between the first substructure of the first interconnect structure and the second substructure of the second interconnect structure is less than a second distance between the first substructure of the first interconnect structure and the first substructure of the second interconnect structure.

8. The circuit of claim 7 , wherein a third distance between the first substructure of the second interconnect structure and the second substructure of the first interconnect structure is greater than the second distance.

9. The circuit of claim 7 , wherein a third distance between the first substructure of the second interconnect structure and the second substructure of the first interconnect structure is greater than the first distance.

10. The circuit of claim 9 , wherein the third distance is greater than the second distance.

11. The circuit of claim 1 , wherein the first and second interconnect structures are electrically insulated from each other at both the first level and the second level.

12. The circuit of claim 1 , wherein the substrate includes a source region of a transistor and a drain region of said transistor, and wherein the first interconnect structure is electrically connected to the source region and wherein the second interconnect structure is electrically connected to the drain region.

13. An integrated circuit, comprising:

a substrate; and

conductive interconnect structures over the substrate, said conductive interconnect structures including a first interconnect structure and a second interconnect structure; and

wherein:

the first interconnect structure is adjacent the second interconnect structure;

the second substructure of the first interconnect structure is electrically coupled to the first substructure of the first interconnect structure;

the second interconnect structure includes a first substructure at the first level and a second substructure at the second level;

the second substructure of the second interconnect structure is electrically coupled to the first substructure of the second interconnect structure; and

wherein a first distance between the first substructure of the first interconnect structure and the second substructure of the second interconnect structure is less than a second distance between the first substructure of the first interconnect structure and the first substructure of the second interconnect structure.

14. The circuit of claim 13 , wherein a third distance between the first substructure of the second interconnect structure and the second substructure of the first interconnect structure is greater than the second distance.

15. The circuit of claim 13 , wherein a third distance between the first substructure of the second interconnect structure and the second substructure of the first interconnect structure is greater than the first distance.

16. The circuit of claim 15 , wherein the third distance is greater than the second distance.

17. The circuit of claim 13 , wherein the first substructure of the first interconnect structure has a length greater than a length of the first substructure of the second interconnect structure, and the second substructure of the second interconnect structure has a length greater than a length of the second substructure of the first interconnect structure.

18. An integrated circuit, comprising:

a substrate; and

conductive interconnect structures over the substrate, said conductive interconnect structures including a first interconnect structure and a second interconnect structure; and

wherein:

the first interconnect structure is adjacent to the second interconnect structure;

the second substructure of the first interconnect structure is electrically coupled to the first substructure of the first interconnect structure;

the second interconnect structure includes a first substructure at the first level and a second substructure at the second level;

the second substructure of the second interconnect structure is electrically coupled to the first substructure of the second interconnect structure;

the first substructure of the first interconnect structure has a length greater than a length of the first substructure of the second interconnect structure;

the second substructure of the second interconnect structure having a length greater than a length of the second substructure of the first interconnect structure; and

19. The circuit of claim 18 , wherein a third distance between the first substructure of the second interconnect structure and the second substructure of the first interconnect structure is greater than the second distance.

20. The circuit of claim 19 , wherein a third distance between the first substructure of the second interconnect structure and the second substructure of the first interconnect structure is greater than the first distance.

21. The circuit of claim 20 , wherein the third distance is greater than the second distance.

22. The circuit of claim 18 , wherein the second substructure of the first structure is in physical contact with the first substructure of the first interconnect structure, and wherein the second substructure of the second interconnect structure is in physical contact with the first substructure of the second interconnect structure.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2024

From: STMICROELECTRONICS, INC.

To: STMICROELECTRONICS INTERNATIONAL N.V.

Reel/Frame 068814/0783 →

Continuity (2)

Continuation 14724975 · May 29, 2015

Related Publication 20170194244A1 · Jul 6, 2017