IP Library Granted Patent US 10,074,611
Granted Patent B1
US 10,074,611 · App. 15/452,888 · Granted Sep 11, 2018

Semiconductor device and method of forming backside openings for an ultra-thin semiconductor die

Inventor: Gordon M. Grivna (Mesa, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/544H01L21/78H01L23/585H01L2223/5446
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Quick Facts
Patent No.
US 10,074,611
App. No.
15/452,888
Granted
Sep 11, 2018
Kind
B1
Abstract

A semiconductor substrate contains a plurality of openings extending partially into a surface of the semiconductor substrate. A conductive layer is formed with a first portion of the conductive layer over a remaining portion of the surface of the semiconductor substrate between the openings and a second portion of the conductive layer in the openings. The remaining portion of the surface of the semiconductor substrate is removed to lift-off the first portion of the conductive layer while leaving the second portion of the conductive layer in the openings. The semiconductor substrate is singulated to separate the semiconductor die leaving the second portion of the conductive layer over a surface of the semiconductor die. Alternatively, a plurality of openings is formed over each semiconductor die. A conductive layer is formed over a remaining portion of the surface of the semiconductor substrate between the openings and into the openings.

Claims (31)

1. A method of making a semiconductor device, comprising:

providing a semiconductor substrate;

forming a plurality of openings extending partially into a surface of the semiconductor substrate to form a flat bottom surface in the openings;

forming a conductive layer including a first portion of the conductive layer over a remaining portion of the semiconductor substrate between the openings and a second portion of the conductive layer over the flat bottom surface in the openings; and

removing the first portion of the conductive layer and at least a portion of the remaining portion of semiconductor substrate while leaving the second portion of the conductive layer over the flat bottom surface in the openings.

2. The method of claim 1 , further including singulating the semiconductor substrate to separate a plurality of semiconductor die formed on the semiconductor substrate leaving the second portion of the conductive layer over a surface of the semiconductor die.

3. The method of claim 2 , wherein a first opening of the plurality of openings is aligned with a first semiconductor die of the plurality of second semiconductor die.

4. The method of claim 2 , wherein forming the plurality of openings reduces a thickness of the plurality of semiconductor die.

5. The method of claim 1 , wherein a thickness of the conductive layer is about 20-50 micrometers.

6. The method of claim 1 , further including forming a support ring around the semiconductor substrate.

7. A method of making a semiconductor device, comprising:

providing a semiconductor substrate including a plurality of semiconductor die;

forming a plurality of openings over each semiconductor die and extending partially into a surface of the semiconductor substrate to form a flat bottom surface in the openings; and

forming a conductive layer over a remaining portion of the surface of the semiconductor substrate between the openings and over the flat bottom surface in the openings.

8. The method of claim 7 , further including singulating the semiconductor substrate to separate the semiconductor die.

9. The method of claim 7 , wherein the remaining portion of the surface of the semiconductor substrate between the openings includes a honeycomb pattern.

10. The method of claim 7 , wherein the remaining portion of the surface of the semiconductor substrate between the openings includes a pattern or shape.

11. The method of claim 7 , wherein forming the plurality of openings reduces a thickness of the plurality of semiconductor die.

12. The method of claim 7 , wherein a thickness of the conductive layer is less than 1.5 micrometers.

13. The method of claim 7 , further including forming a support ring around the semiconductor substrate.

14. A method of making a semiconductor device, comprising:

providing a semiconductor substrate including a plurality of semiconductor die;

forming a plurality of openings over each semiconductor die and extending partially into a surface of the semiconductor substrate to form a flat bottom surface in the openings; and

forming a conductive layer over a remaining portion of the semiconductor substrate between the openings and over the flat bottom surface in the openings; and

removing the first portion of the conductive layer and at least a portion of the remaining portion of semiconductor substrate while leaving the conductive layer over the flat bottom surface in the openings.

15. The method of claim 14 , further including disposing the plurality of openings formed over each semiconductor die in multiple offset rows.

16. The method of claim 14 , wherein the remaining portion of the surface of the semiconductor substrate between the openings includes a honeycomb pattern.

17. The method of claim 14 , wherein the remaining portion of the surface of the semiconductor substrate between the openings includes a pattern or shape.

18. The method of claim 14 , wherein the plurality of openings reduces a thickness of the plurality of semiconductor die.

19. The method of claim 14 , wherein a thickness of the conductive layer is less than 1.5 micrometers.

20. The method of claim 14 , wherein the plurality of semiconductor die is offset on the semiconductor substrate.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 04481, FRAME 0541 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0459 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2017
From: GRIVNA, GORDON M.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 041500/0675 →
Cited By (1)
US 12,394,617