IP Library › Granted Patent US 12,394,617
Granted Patent B2
US 12,394,617 · App. 17/679,010 · Granted Aug 19, 2025

Manufacturing method of semiconductor apparatus

Inventor: Michiya Kitano (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L21/02013H01L21/02019
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Quick Facts
Patent No.
US 12,394,617
App. No.
17/679,010
Granted
Aug 19, 2025
Kind
B2
Abstract

Provided is a manufacturing method of semiconductor apparatus comprising a semiconductor substrate, the method comprising: grinding a first surface of the semiconductor substrate to form an outer peripheral surplus region on an outer periphery of the semiconductor substrate; and spin etching the first surface of the semiconductor substrate by a chemical liquid, and wherein after the grinding, in a region of the semiconductor substrate which is closer to an inner side than the outer peripheral surplus region, a thickness of the semiconductor substrate in an end portion of the region is greater than a thickness of the semiconductor substrate in a center portion of the region.

Claims (23)

1. A manufacturing method of a semiconductor apparatus comprising a semiconductor substrate, the method comprising:

grinding a first surface of the semiconductor substrate to form an outer peripheral surplus region that coincides in location with an outer periphery of the semiconductor substrate; and

spin etching a ground surface, formed by grinding the first surface of the semiconductor substrate, by a chemical liquid, and wherein

after the grinding, a region inward of the outer peripheral surplus region is formed, a thickness of the semiconductor substrate in an end portion of the region inward of the outer peripheral surplus region is greater than a thickness of the semiconductor substrate in a center portion of the region inward of the outer peripheral surplus region,

after the grinding, the semiconductor substrate has a slope portion, located in the region inward of the outer peripheral surplus region, that contacts the outer peripheral surplus region, the slope portion has a maximum height, the outer peripheral surplus region rises in a direction perpendicular to a plane defined by a radial direction of the semiconductor substrate and a circumferential direction of the semiconductor substrate to a height greater than the maximum height of the slope portion where the slope portion contacts the outer peripheral surplus region.

2. The manufacturing method of the semiconductor apparatus according to claim 1 , wherein an inclination angle of the slope portion is 1 degree or less.

3. The manufacturing method of the semiconductor apparatus according to claim 1 , wherein a height of the slope portion is 20 μm or less.

4. The manufacturing method of the semiconductor apparatus according to claim 2 , wherein a height of the slope portion is 20 μm or less.

5. The manufacturing method of the semiconductor apparatus according to claim 1 , wherein a width of the slope portion is 15 mm or more.

6. The manufacturing method of the semiconductor apparatus according to claim 2 , wherein a width of the slope portion is 15 mm or more.

7. The manufacturing method of the semiconductor apparatus according to claim 1 , wherein a width of the slope portion is 10% or more of a radius of the semiconductor substrate.

8. The manufacturing method of the semiconductor apparatus according to claim 2 , wherein a width of the slope portion is 10% or more of a radius of the semiconductor substrate.

9. The manufacturing method of the semiconductor apparatus according to claim 1 , wherein the semiconductor substrate has a diameter of 300 mm or more.

10. The manufacturing method of the semiconductor apparatus according to claim 1 , wherein in the grinding, the semiconductor substrate is ground by inclining a whetstone with respect to a radial direction of the semiconductor substrate.

11. The manufacturing method of the semiconductor apparatus according to claim 1 , wherein in the grinding, the semiconductor substrate is ground by moving a whetstone from the end portion of the region to the center portion of the region.

12. The manufacturing method of the semiconductor apparatus according to claim 10 , wherein a diameter of the whetstone is greater than a radius of the region.

13. The manufacturing method of the semiconductor apparatus according to claim 11 , wherein a diameter of the whetstone is greater than a radius of the region.

14. A manufacturing method of a semiconductor apparatus comprising a semiconductor substrate, the method comprising:

grinding a first surface of the semiconductor substrate to form an outer peripheral surplus region that coincides in location with an outer periphery of the semiconductor substrate; and

spin etching a ground surface, formed by grinding the first surface of the semiconductor substrate, by a chemical liquid, and wherein

after the grinding, a region inward of the outer peripheral surplus region is formed, a thickness of the semiconductor substrate in an end portion of the region inward of the outer peripheral surplus region is greater than a thickness of the semiconductor substrate in a center portion of the region inward of the outer peripheral surplus region,

during the grinding, the semiconductor substrate is ground using a whetstone that is rotated about an axis of rotation and has a grinding surface that participates in the grinding, the axis of rotation of the whetstone is perpendicular to the grinding surface, and the grinding surface is inclined with respect to one of a radial direction of the semiconductor substrate and a circumferential direction of the semiconductor substrate.

15. The manufacturing method of the semiconductor apparatus according to claim 14 , wherein in the grinding, the semiconductor substrate is ground by inclining the grinding surface of the whetstone with respect to a circumferential direction of the semiconductor substrate, and a diameter of the whetstone is 110% or more and 130% or less of a radius of the region inward of the outer peripheral surplus region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2022
From: KITANO, MICHIYA
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 059235/0538 →
Priority Claims (1)
JP 2021-071773 · Apr 21, 2021 · national
Continuity (1)
Related Publication 20220344149A1 · Oct 27, 2022
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