Wafer level package (WLP) and method for forming the same

1. A semiconductor device, comprising:

a substrate;

a conductive pad formed on the substrate;

a first protection layer formed over the conductive pad;

a second protection layer formed over the first protection layer;

a post-passivation interconnect (PPI) structure having a first region extending into the first protection layer and having a second region extending over an uppermost surface of the second protection layer; and

a first moisture-resistant layer formed over the second protection layer, wherein the second protection layer and the first moisture-resistant layer are made of different materials.

2. The semiconductor device of claim 1 , wherein the first moisture-resistant layer comprises polyimide (PI), epoxy, solder resist (SR), silicon nitride, silicon oxide, HMDS (hexamethyldisilazane), fluorine-containing polymer or combinations thereof.

3. The semiconductor device of claim 1 , wherein the first region of the PPI structure includes a PPI pad contacting the conductive pad.

4. The semiconductor device of claim 1 , further comprising:

an under bump metallurgy (UBM) structure formed in an opening in the first moisture-resistant layer; and

a second moisture-resistant layer formed over the first moisture-resistant layer and adjacent to the UBM layer.

5. The semiconductor device of claim 4 , wherein the second moisture-resistant layer is made of fluorine-containing polymer, wherein the fluorine-containing polymer comprises carbon-fluorine (C—F) bonds with a range from about 30 wt % to about 60 wt %.

6. The semiconductor device of claim 1 , further comprising:

a passivation layer formed between the conductive pad and the PPI structure, wherein the passivation layer and the first moisture-resistant layer are made of the same material.

7. The semiconductor device of claim 1 , further comprising an insulating layer surrounding a periphery of the substrate, wherein the second protection layer and the moisture-resistant layer extend over the insulating layer.

8. The semiconductor device of claim 1 , wherein the first moisture-resistant layer comprises a polymer having a decomposition temperature of between about 250 degrees and about 400 degrees and a glass transition temperature of between about 200 degrees and about 350 degrees.

9. The semiconductor device of claim 1 , wherein the first moisture-resistant layer has a water absorption ranging from about 0.5 wt % to about 2.5 wt %.

10. A method comprising:

forming a conductive pad over a substrate;

depositing a first protection layer over the conductive pad;

depositing a second protection layer over the first protection layer;

forming a post-passivation interconnect (PPI) structure electrically connected to the conductive pad, wherein the PPI structure extends from a topmost surface of the second protection layer to a bottommost surface of the second protection layer; and

forming a first moisture-resistant layer over the second protection layer, wherein the first protection layer and the first moisture resistant are made of different materials.

11. The method of claim 10 , further comprising forming an under bump metallurgy (UBM) layer in the first moisture-resistant layer.

12. The method of claim 11 , further comprising forming a fluorine-containing polymer layer adjacent to the UBM layer.

13. The method of claim 10 , wherein the first moisture-resistant layer has a water absorption ranging from about 0.5 wt % to about 2.5 wt %.

14. The method of claim 10 , further comprising:

forming an integrated circuit between the conductive pad and the substrate;

forming an insulating layer surrounding the integrated circuit; and

forming a conductive pillar structure through the insulating layer and adjacent to the integrated circuit.

15. The method of claim 14 , further comprising depositing the first moisture-resistant layer over the insulating layer.

16. The method of claim 10 , wherein forming a first moisture-resistant layer includes depositing a polymer having a decomposition temperature of from about 250 degrees to about 400 degrees and a glass transition temperature of from about 200 degrees to about 350 degrees.

17. A structure comprising:

a conductive pad on a major surface of a substrate;

a first patterned protection layer extending over the conductive pad and having a first opening therein exposing the conductive pad;

a second patterned protection layer extending over the first patterned protection layer and having an opening therein aligned to the first opening;

a wiring structure at least partially embedded in the second patterned protection layer and at least partially extending over a topmost surface of the second patterned protection layer; and

a patterned moisture-resistant layer extending over the wiring structure and over the second patterned protection layer, the patterned moisture-resistant layer having an opening therein exposing the wiring structure, the patterned moisture-resistant layer having a water absorption property that is less than a water absorption property of the first patterned protection layer and the second patterned protection layer, respectively.

18. The structure of claim 17 , further comprising an under bump metallurgy (UBM) layer formed over the patterned moisture-resistant layer and connected to the wiring structure.

19. The structure of claim 17 , wherein the second patterned moisture-resistant layer comprises polyimide (PI), epoxy, solder resist (SR), silicon nitride, silicon oxide, HMDS (hexamethyldisilazane), fluorine-containing polymer or combinations thereof.

20. The structure of claim 17 , wherein the second patterned protection layer is made of polybenzoxazole (PBO), and the first moisture-resistant layer is made of polyimide (PI), wherein the polyimide (PI) comprises cross-links with a range from about 10 wt % to about 40 wt %.