IP Library Granted Patent US 10,074,721
Granted Patent B2
US 10,074,721 · App. 15/273,231 · Granted Sep 11, 2018

Method of fabricating a semiconductor wafer that includes producing a planarised surface having both a mesa surface and an insulating layer surface

Inventors: Albert Birner (Regensburg, DE); Helmut Brech (Lappersdorf, DE); Simone Lavanga (Faak am See, AT)
Assignee: Infineon Technologies AG
H01L29/205H01L21/0254H01L21/304H01L21/31053H01L21/31056H01L21/76229H01L29/2003H01L21/02378H01L21/02381H01L21/02433H01L29/66462H01L29/778
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Quick Facts
Patent No.
US 10,074,721
App. No.
15/273,231
Granted
Sep 11, 2018
Kind
B2
Abstract

In an embodiment, a method of planarizing a surface includes applying a first layer to a surface including a protruding region such that the first layer covers the surface and the protruding region, removing a portion of the first layer above the protruding region and forming an indentation in the first layer above the protruding region, the protruding region remaining covered by material of the first layer, and progressively removing an outermost surface of the first layer to produce a planarised surface.

Claims (27)

1. A method of planarising a surface, the method comprising:

applying a first layer to a surface comprising a protruding semiconductor region such that the first layer covers the surface and the protruding semiconductor region;

removing a portion of the first layer above the protruding semiconductor region and forming an indentation in the first layer above the protruding semiconductor region, the protruding semiconductor region remaining covered by material of the first layer; and

progressively removing an outermost surface of the first layer to produce a planarised surface so that an upper surface of the protruding semiconductor region underlying the first layer is revealed.

2. The method of claim 1 , wherein the outermost surface of the first layer is progressively removed by chemical mechanical polishing.

3. The method of claim 1 , wherein an initial thickness of the first layer above the protruding semiconductor region is reduced by 80% to 90% to form the indentation.

4. The method of claim 1 , further comprising:

forming a structured mask on the first layer having an opening above the protruding semiconductor region, the opening having a lateral area smaller than a lateral area of the protruding semiconductor region;

removing a portion of the first layer within the opening to form the indentation in the first layer; and

removing the mask.

5. The method of claim 4 , wherein the first layer and the structured mask provide a protrusion at edges of the protruding semiconductor region.

6. A method of fabricating a semiconductor wafer, the method comprising:

depositing an insulating layer onto a substrate comprising at least one mesa comprising at least one Group III nitride such that an upper surface of the substrate and the mesa are covered with the insulating layer;

forming a structured mask on the insulating layer having an opening above the mesa, the opening having a lateral area smaller than a lateral area of the mesa;

removing a portion of the insulating layer within the opening and reducing a thickness of the insulating layer arranged above the mesa; and

removing the mask and portions of the insulating layer to produce a planarised surface comprising a surface of the mesa and a surface of the insulating layer.

7. The method of claim 6 , further comprising forming the at least one mesa comprising the at least one Group III nitride by removing regions of a layer comprising at least one Group-III nitride arranged on the substrate.

8. The method of claim 7 , wherein removing regions of the layer comprising at least one Group III nitride further comprises exposing a surface of the substrate.

9. The method of claim 7 , further comprising:

applying a stop layer onto the at least one Group III nitride;

applying a sacrificial layer onto the stop layer;

applying a structured mask to the sacrificial layer having openings; and

removing the sacrificial layer in the openings to expose discrete areas of the stop layer.

10. The method of claim 9 , further comprising removing portions of the stop layer and the at least one Group III nitride in regions uncovered by the sacrificial layer to form at least one mesa on a surface of the substrate.

11. The method of claim 6 , wherein removing the mask and reducing the thickness of the insulating layer comprises progressively removing the insulating layer by chemical mechanical polishing.

12. The method of claim 6 , wherein removing the portion of the insulating layer within the opening comprises forming an indentation in the insulating layer with the insulating layer covering the mesa.

13. The method of claim 6 , wherein the insulating layer and the structured mask provide a protrusion above edges of the mesa.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2016
From: BIRNER, ALBERT; BRECH, HELMUT; LAVANGA, SIMONE
To: INFINEON TECHNOLOGIES AG
Reel/Frame 039836/0042 →
Continuity (1)
Related Publication 20180083107A1 · Mar 22, 2018