IP Library › Granted Patent US 10,079,155
Granted Patent B2
US 10,079,155 · App. 15/643,002 · Granted Sep 18, 2018

Semiconductor device manufacturing method

Inventors: Tsunehiro Nakajima (Matsumoto, JP); Yoshikazu Takahashi (Matsumoto, JP); Norihiro Nashida (Nagano, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L21/32115H01L21/283H01L21/6835H01L21/6836H01L23/3735H01L23/482H01L23/492H01L24/24H01L24/34H01L25/0652H01L25/50H01L23/49811H01L2221/6834H01L2221/68327H01L2224/24137
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Quick Facts
Patent No.
US 10,079,155
App. No.
15/643,002
Granted
Sep 18, 2018
Kind
B2
Abstract

A semiconductor device manufacturing method, sequentially includes a semiconductor element preparation step of preparing a first semiconductor element on which is formed a plurality of metal electrodes, a step of covering a surface of the first semiconductor element on which the metal electrode is not formed with a first insulating member, and a step of forming a second metal layer that conductively connects the metal electrode of the first semiconductor element and a first metal layer on an insulated circuit substrate across the second insulating member.

Claims (12)

1. A semiconductor device manufacturing method, sequentially comprising:

a semiconductor element preparation step of preparing a semiconductor element on which is formed a plurality of metal electrodes;

a step of disposing another metal electrode of the semiconductor element so as to block a through hole of a metal plate;

a spraying step of spraying metal onto the another metal electrode of the semiconductor element from the through hole in a surface of the metal plate on a side opposite to a surface with the semiconductor element;

a polishing step of polishing a surface of the sprayed metal;

a step of covering a surface of the semiconductor element on which the plurality of metal electrodes is not formed with a first insulating member; and

a step of forming a second metal layer that conductively connects the plurality of metal electrodes of the semiconductor element and a first metal layer on an insulated circuit substrate across the first insulating member.

2. The semiconductor device manufacturing method according to claim 1 , wherein the second metal layer is formed by spraying metal.

3. The semiconductor device manufacturing method according to claim 1 , before the polishing step, further sequentially comprising:

a step of disposing a second insulating member that fixes the metal plate and the semiconductor element in a position on the metal plate in which the semiconductor element is not disposed; and

a step of covering with a protective tape the surface of the semiconductor element and a surface of the second insulating member, each of the surfaces of the semiconductor element and second insulating member being opposite to a side facing the metal plate.

4. The semiconductor device manufacturing method according to claim 1 , further comprising a step of directly joining the polished surface of the metal and a third metal layer on the insulated circuit substrate.

Priority Claims (1)
JP 2015-161392 · Aug 18, 2015 · national
Continuity (2)
Division 15205596 · Jul 8, 2016
Related Publication 20170309496A1 · Oct 26, 2017
Cited By (1)
US 12,690,456