FET with local isolation layers on S/D trench sidewalls
A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure. The method also includes forming trenches in the semiconductor substrate at outside of the gate structure; and forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions. Further, the method includes removing at least portions of the offset sidewall spacers to expose portions of the surface of the semiconductor substrate between the gate structure and the trenches; and forming filling layers with a top surface higher than the surface of the semiconductor substrate by filling the trenches and covering portions of the surface of the semiconductor substrate between the trenches and the gate structure. Further, the method also includes forming doping regions configured as raised source/drain regions in the filling layers.
1. A semiconductor device, comprising:
a semiconductor substrate having a first surface;
a gate structure formed on the first surface of the semiconductor substrate, the gate structure being in direct contact with the first surface;
offset sidewall spacers covering side surfaces of the gate structure;
filling layers formed in the semiconductor substrate at outside of the gate structure and on portions of the first surface of the semiconductor substrate between the offset sidewall spacers of the gate structure and side surfaces of the filling layers;
doping regions configured as raised source/drain regions formed in the filling layers; and
isolation layers formed between side surfaces of the filling layers and the semiconductor substrate to prevent diffusions between the doping regions,
wherein the isolation layers have top surfaces, the top surfaces of the isolation layers being coplanar with the first surface, wherein the offset sidewall spacers and the isolation layers are not in direct contact with each other,
wherein the filling layers are formed by: forming trenches in the semiconductor substrate at outside of the gate structure; forming isolation layers on side surfaces of the trenches; and filling up the trenches;
isolation structures formed in the semiconductor substrate and located outside of the isolation layers on both sides of the gate structure, the isolation structures being in direct contact with the isolation layers, wherein the offset sidewall spacers are multiple-stacked structures comprising a silicon oxide layer and a silicon nitride layer.
2. The semiconductor device according to claim 1 , wherein:
the doped regions include lightly doped regions and heavily doped regions; and
surfaces of the doping regions are higher than the surface of the semiconductor substrate so as to be configured as the raised source/drain regions.
3. The semiconductor device according to claim 1 , wherein:
the isolation layers are made of silicon oxide, silicon nitride or silicon oxynitride.
4. The semiconductor device according to claim 1 , wherein:
the filling layers are made of Si, SiGe, SiGeB, SiC, or SiCP.
5. The semiconductor device according to claim 1 , wherein:
metal silicide layers are formed on the filling layers.
6. A semiconductor device, comprising:
a semiconductor substrate having a first surface;
a gate structure formed on the first surface of the semiconductor substrate;
offset sidewall spacers covering side surfaces of the gate structure;
filling layers formed in the semiconductor substrate at outside of the gate structure and on portions of the first surface of the semiconductor substrate between the offset sidewall spacers of the gate structure and side surfaces of the filling layers;
doping regions configured as raised source/drain regions formed in the filling layers; and
isolation layers formed between side surfaces of the filling layers and the semiconductor substrate to prevent diffusions between the doping regions, wherein
the filling layers are formed by: forming trenches in the semiconductor substrate at outside of the gate structure; forming isolation layers on side surfaces of the trenches; and filling up the trenches,
the filling layers with a top surface higher than the first surface cover portions of the first surface of the semiconductor substrate between the trenches and the gate structure, and
the isolation layers have a uniform thickness along an entirety of the side surfaces of the trenches, and the isolation layers are not formed on a bottom of the trenches.
7. The semiconductor device according to claim 6 , wherein:
the doped regions include lightly doped regions and heavily doped regions; and
surfaces of the doping regions are higher than the surface of the semiconductor substrate so as to be configured as the raised source/drain regions.
8. The semiconductor device according to claim 6 , wherein:
the isolation layers are made of silicon oxide, silicon nitride or silicon oxynitride.
9. The semiconductor device according to claim 6 , wherein:
the filling layers are made of Si, SiGe, SiGeB, SiC, or SiCP.
10. The semiconductor device according to claim 6 , wherein:
metal silicide layers are formed on the filling layers.
11. The semiconductor device according to claim 6 , wherein:
the offset sidewall spacers are multiple-stacked structures comprising a silicon oxide layer and a silicon nitride layer.