IP Library Granted Patent US 10,079,302
Granted Patent B2
US 10,079,302 · App. 14/979,720 · Granted Sep 18, 2018

Silicon germanium fin immune to epitaxy defect

Inventors: Kangguo Cheng (Schenectady, NY); Juntao Li (Cohoes, NY); Xin Miao (Guilderland, NY)
Assignee: International Business Machines Corporation
H01L29/7848H01L29/0847H01L29/161H01L29/165H01L29/66545H01L29/66803H01L29/7851
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Quick Facts
Patent No.
US 10,079,302
App. No.
14/979,720
Granted
Sep 18, 2018
Kind
B2
Abstract

A method for forming a semiconductor structure includes forming at least one fin on a semiconductor substrate. The least one fin includes a semiconducting material. A gate is formed over and in contact with the at least one fin. A germanium comprising layer is formed over and in contact with the at least one fin. Germanium from the germanium comprising layer is diffused into the semiconducting material of the at least one fin.

Claims (20)

1. A method of forming a semiconductor structure, the method comprising:

forming at least one fin on a semiconductor substrate, the least one fin comprising a semiconducting material;

forming a gate over and in contact with the at least one fin, wherein the gate is a dummy gate;

depositing a germanium comprising layer over and in contact with an exposed top surface the at least one fin;

diffusing germanium from the germanium comprising layer into the semiconducting material of the at least one fin;

after the diffusing, removing the dummy gate;

after removing the dummy gate, forming a gate stack over and in contact with the at least one fin; and

after forming the gate stack, forming a source region and a drain region in contact with the at least one fin, wherein forming the source region and the drain region comprises

epitaxially growing a semiconductor material on at least sidewalls of the at least one fin, and

forming the source region and the drain region in the at least one epitaxially grown semiconductor material.

2. The method of claim 1 wherein forming the gate stack comprises: forming a dielectric layer over and in contact with the at least one fin.

3. The method of claim 2 , wherein forming the gate stack further comprises:

after forming the gate dielectric layer, forming a gate conductor layer over and in contact with the gate dielectric layer.

4. The method of claim 3 , further comprising:

forming a spacer layer on sidewalls of the gate stack.

5. The method of claim 1 , further comprising: after forming the gate stack, forming a source region and a drain region in contact with the at least one fin.

6. The method of claim 1 , further comprising: forming a spacer layer in contact with the dummy gate, wherein the gate stack is formed in contact with the spacer layer after the dummy gate has been removed.

7. The method of claim 1 , further comprising:

forming a nitride layer on an in contact with the gate.

8. The method of claim 1 , wherein the germanium comprising layer is deposited prior to forming the source region and the drain region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2015
From: CHENG, KANGGUO; LI, JUNTAO; MIAO, XIN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037362/0976 →
Continuity (1)
Related Publication 20170186868A1 · Jun 29, 2017