Semiconductor devices including field effect transistors and methods of fabricating the same
A semiconductor device includes a fin structure on a substrate, device isolation patterns on the substrate at opposite sides of the fin structure, a gate electrode intersecting the fin structure and the device isolation patterns, a gate dielectric pattern between the gate electrode and the fin structure and between the gate electrode and the device isolation patterns, and gate spacers on opposite sidewalls of the gate electrode, wherein, on each of the device isolation patterns, a bottom surface of the gate dielectric pattern is at a higher level than bottom surfaces of the gate spacers.
1. A semiconductor device, comprising:
a fin structure on a substrate;
device isolation patterns on the substrate at opposite sides of the fin structure;
a gate electrode intersecting the fin structure and the device isolation patterns;
a gate dielectric pattern completely separating between the gate electrode and the fin structure and between the gate electrode and the device isolation patterns; and
gate spacers on opposite sidewalls of the gate electrode,
wherein, on each of the device isolation patterns, a bottom surface of the gate dielectric pattern is at a higher level than an entire bottom surface of each gate spacer of the gate spacers that contacts the device isolation pattern,
wherein, on a topmost surface of the fin structure, the bottom surface of the gate dielectric pattern is level with the entire bottom surface of each gate spacer of the gate spacers.
2. The semiconductor device as claimed in claim 1 , wherein:
the gate electrode and the gate dielectric pattern define a gate structure, and
each of the device isolation patterns includes:
a first portion under the gate structure, and
second portions at opposite sides of the gate structure, a top surface of the first portion being at a higher level than top surfaces of the second portions.
3. The semiconductor device as claimed in claim 2 , wherein at least a portion of the first portion is between the gate spacers.
4. The semiconductor device as claimed in claim 2 , wherein the bottom surface of the gate dielectric pattern is in contact with the top surface of the first portion, and the bottom surfaces of the gate spacers are in contact with the top surfaces of the second portions, respectively.
5. The semiconductor device as claimed in claim 4 , wherein the gate dielectric pattern extends between the gate electrode and the gate spacers.
6. The semiconductor device as claimed in claim 2 , wherein the topmost surface of the fin structure is at a higher level than a topmost surface of each of the device isolation patterns.
7. The semiconductor device as claimed in claim 2 , wherein the fin structure includes:
a third portion under the gate structure and the gate spacers; and
fourth portions at opposite sides of the gate structure to be laterally spaced apart from each other with the third portion interposed therebetween,
wherein a top surface of the third portion is at a higher level than top surfaces of the fourth portions,
wherein the top surface of the first portion is at a lower level than the top surface of the third portion, and
wherein source/drain regions are positioned on the fourth portions of the fin structure, respectively.
8. The semiconductor device as claimed in claim 1 , wherein, on a topmost surface of the fin structure, the bottom surface of the gate dielectric pattern is level with the bottom surfaces of the gate spacers.
9. A semiconductor device, comprising:
a fin structure on a substrate and extending in a first direction;
device isolation patterns on the substrate at opposite sides of the fin structure, respectively;
a gate electrode on the fin structure and the device isolation patterns, and extending in a second direction intersecting the first direction;
source/drain regions at opposite sides of the gate electrode; and
gate spacers on opposite sidewalls of the gate electrode, respectively, and conformal on top and side surfaces of the fin structure, each gate spacer of the gate spacers being between the gate electrode and a corresponding one of the source/drain regions,
wherein each of the device isolation patterns includes a first portion between portions of facing surfaces of the gate spacers,
wherein the fin structure includes a third portion under the gate electrode and the gate spacers, the third portion being interposed between the source/drain regions, and
wherein a width of a top surface of the third portion in the first direction is greater than a width of a top surface of the first portion in the first direction.
10. The semiconductor device as claimed in claim 9 , further comprising:
a gate dielectric pattern between the gate electrode and the fin structure, the gate dielectric pattern extending between the gate electrode and each of the device isolation patterns,
wherein the gate electrode and the gate dielectric pattern define a gate structure,
wherein each of the device isolation patterns further includes
second portions at opposite sides of the gate structure, respectively, and
wherein the top surface of the first portion is at a higher level than top surfaces of the second portions.
11. The semiconductor device as claimed in claim 10 , wherein a bottom surface of the gate dielectric pattern is in contact with the top surface of the first portion.
12. The semiconductor device as claimed in claim 11 , wherein the gate dielectric pattern extends between the gate electrode and the gate spacers.
13. The semiconductor device as claimed in claim 10 , wherein bottom surfaces of the gate spacers are in contact with the top surfaces of the second portions, respectively.
14. The semiconductor device as claimed in claim 10 , wherein the fin structure further includes
fourth portions at opposite sides of the gate structure to be laterally spaced apart from each other with the third portion interposed therebetween,
wherein the top surface of the third portion is at a higher level than top surfaces of the fourth portions, and
wherein the top surface of the first portion is at a lower level than the top surface of the third portion.
15. The semiconductor device as claimed in claim 14 , wherein the source/drain regions are on the fourth portions of the fin structure, respectively.
16. A semiconductor device, comprising:
a fin structure on a substrate;
device isolation patterns on the substrate at opposite sides of the fin structure;
a gate electrode intersecting the fin structure and the device isolation patterns;
a gate dielectric pattern between the fin structure and the gate electrode; and
gate spacers on opposite sidewalls of the gate electrode,
wherein a first portion of each of the device isolation patterns protrudes toward the gate electrode and separates between the gate spacers,
wherein the gate dielectric pattern includes an extending portion that vertically extends from the first portion and between the gate electrode and each gate spacer of the gate spacers, and
wherein an outer surface of the extending portion is vertically aligned with an outer surface of an upper sidewall of the first portion.
17. The semiconductor device as claimed in claim 16 , wherein the gate spacers extend beyond the opposite sidewalls of the gate electrode toward the substrate.
18. The semiconductor device as claimed in claim 16 , wherein the gate spacers overlap the sidewalls of the gate electrode and sidewalls of the first portion of each of the device isolation patterns.
19. The semiconductor device as claimed in claim 16 , wherein each of device isolation patterns includes:
the first portion only in a region overlapping the gate electrode; and
second portions at opposite sides of the first portion, the first portion extending above the second portions into a space between the gate spacers.
20. The semiconductor device as claimed in claim 16 , wherein a distance between a bottom of the gate electrode and a bottom of the substrate is larger than a distance between bottoms of the gate spacers and the bottom of the substrate.