Semiconductor structure and manufacturing method of the same
The present disclosure provide a semiconductor structure, including a substrate having a top surface; a gate over the substrate, the gate including a footing region in proximity to the top surface, the footing region including a footing length laterally measured at a height under 10 nm above the top surface; and a spacer surrounding a sidewall of the gate, including a spacer width laterally measured at a height of from about 10 nm to about 200 nm above the top surface. The footing length is measured, along the top surface, from an end of a widest portion of the footing region to a vertical line extended from an interface between a gate body and the spacer, and the spacer width is substantially equal to or greater than the footing length.
1. A semiconductor structure, comprising:
a substrate having a top surface;
a gate over the substrate, comprising:
a gate dielectric in proximity to the top surface; and
a gate body further away from the top surface,
wherein the gate dielectric is between the gate body and the top surface, the gate dielectric further comprising a footing region comprising a footing length laterally measured at a height under 10 nm above the top surface, the footing region having a widest portion in proximity to the substrate and a narrowest portion away from the substrate; and
a spacer surrounding a sidewall of the gate body and overlying the footing region, comprising a spacer width laterally measured above the narrowest portion of the footing region,
wherein the footing length is measured, along the top surface, from an end of the widest portion of the footing region to a vertical line extended from an interface between the gate body and the spacer, and
wherein the spacer width is greater than the footing length, and the spacer is free from contacting the footing region.
2. The semiconductor structure of claim 1 , wherein the gate dielectric comprises a high-K dielectric layer over the top surface.
3. The semiconductor structure of claim 2 , wherein the gate comprises the high-K dielectric layer at the sidewall of the gate.
4. The semiconductor structure of claim 1 , wherein the spacer width is in a range of from about 2 nm to about 20 nm.
5. The semiconductor structure of claim 2 , wherein the gate further comprises at least one of an N-work function layer and a P-work function layer.
6. The semiconductor structure of claim 1 , wherein the epitaxy region comprises a first epitaxy region, a measure of a first proximity of the first epitaxy region being equal to or smaller than the spacer width.
7. The semiconductor structure of claim 6 , wherein the epitaxy region comprises a second epitaxy region, a second proximity of the second epitaxy region being substantially identical to the first proximity.
8. A semiconductor structure, comprising:
a substrate having a top surface;
a metal gate over the top surface, the metal gate comprising:
a gate dielectric in proximity to the top surface of the substrate; and
a gate body further away from the top surface,
wherein the gate dielectric is between the gate body and the top surface, the gate dielectric further comprising a footing region having a widest portion in proximity to the top surface of the substrate and a narrowest portion away from the top surface of the substrate;
an epitaxy region partially in the substrate, adjacent to a channel region under the metal gate, and undercutting the footing region, the epitaxy region being doped; and
a spacer surrounding a sidewall of the metal gate, wherein the spacer is free from contacting the footing region.
9. The semiconductor structure of claim 8 , wherein the metal gate comprises a high-K dielectric layer over the top surface.
10. The semiconductor structure of claim 9 , wherein the metal gate comprises the high-K dielectric layer at the sidewall of the metal gate.
11. The semiconductor structure of claim 8 , wherein the footing region comprises a footing length measured, along the top surface, from an end of a widest portion of the footing region to a vertical line extended from an interface between the metal gate and the spacer, and
wherein the spacer comprises a spacer width laterally measured at a height of from about 10 nm to about 200 nm above the top surface, the spacer width being greater than or substantially equal to the footing length.
12. The semiconductor structure of claim 11 , wherein a measure of proximity of the epitaxy region is substantially identical or smaller than the spacer width.
13. The semiconductor structure of claim 8 , wherein the widest portion in proximity to the substrate of the footing region, the spacer, the dielectric layer, and the epitaxy region form a quadruple point.
14. A semiconductor structure, comprising:
a substrate having a top surface;
a gate over the top surface, comprising:
a gate dielectric in proximity to the top surface; and
a gate body further away from the top surface,
wherein the gate dielectric is between the gate body and the top surface, the gate dielectric further comprising a footing region, the footing region having a widest portion in proximity to the substrate and a narrowest portion away from the substrate;
an epitaxy region partially in the substrate, adjacent to a channel region under the gate, and undercutting the footing region, the epitaxy region being doped;
a spacer surrounding a sidewall of the gate; and
a dielectric layer surrounding the spacer,
wherein the footing region is in proximity to the top surface of the substrate, and the spacer comprises a spacer width laterally measured at a height of from about 10 nm to about 200 nm above the top surface,
wherein a length of the footing region is measured along the top surface, from an end of the widest portion of the footing region to a vertical line extended from an interface between the gate body and the spacer, wherein the spacer width is greater than the footing length, and wherein the spacer is free from contacting the footing region.
15. The semiconductor structure of claim 14 , wherein the footing region, the spacer, and the dielectric layer form a triple point.
16. The semiconductor structure of claim 14 , wherein a bottom of the spacer is not in contact with the top surface of the substrate.
17. The semiconductor structure of claim 14 , wherein the gate is a metal gate.
18. The semiconductor structure of claim 14 , wherein the semiconductor structure further comprises a second epitaxy region partially in the substrate, adjacent to a channel region under the gate, a second proximity of the second epitaxy region being equal to or smaller than the spacer width.
19. The semiconductor structure of claim 14 , wherein the spacer width is in a range of from about 2 nm to about 20 nm.