Low power analog-to-digital converter

1. A single slope analog to digital converter (ADC) comprising:

a comparator having a positive input and a negative input and a comparator output;

a counter;

a latch connected to an output of the counter and that includes a trigger input; and

a pulse generator coupled to the comparator output that produces a pulse of a defined width each time a signal on the negative input transitions from a voltage level that is below a voltage level on the positive input to a voltage level that is above the voltage level on the positive input;

wherein the pulse generator includes a pulse generator output coupled to the trigger input and wherein the pulse generator includes a gate having first and second logic gate inputs, the first logic gate input being coupled to the comparator output and the second logic gate input being coupled to a delayed version of the comparator output.

2. The single slope ADC of claim 1 , wherein the delayed version of the comparator output is inverted.

3. The single slope ADC of claim 2 , wherein the pulse generator has a first pulse generator input and further comprises:

a delay element; and

an inverter connected in series with the delay element;

wherein the inverter and the delay element are connected between the first pulse generator input and the second logic gate input.

4. The single slope ADC of claim 1 , wherein the counter is a gray counter.

5. The single slope ADC of claim 1 , wherein the comparator comprises:

a first comparator having first positive and negative inputs and a first comparator output;

a second comparator having second positive and negative inputs and a second comparator output;

wherein the second negative input is connected to the first negative input.

6. A single slope analog to digital converter (ADC) comprising:

a first comparator having a positive input and a negative input and a first comparator output;

a first counter;

a first latch connected to an output of the first counter and that includes a first trigger input; and

a first pulse generator coupled to the first comparator output that produces a pulse of a defined width each time a signal on the negative input of the first comparator transitions from a voltage level that is below a voltage level on the positive input of the first comparator to a voltage level that is above the voltage level on the positive input of the first comparator;

a second comparator having a positive and a negative input and a second comparator output;

a second counter;

a second latch connected to an output of the second counter and that includes a second trigger input; and

a second pulse generator coupled to the second comparator output that produces a pulse of a defined width each time a signal on the negative input of the second comparator transitions from a voltage level that is below a voltage level on the positive input of the second comparator to a voltage level that is above the voltage level on the positive input of the second comparator.

7. The ADC of claim 6 , wherein the first pulse generator includes a first pulse generator output coupled to the trigger input of the first latch and wherein the first pulse generator includes a gate having first and second logic gate inputs, the first logic gate input being coupled to the first comparator output and the second logic gate input being coupled to a delayed version of the first comparator output.

8. The single slope ADC of claim 7 , wherein the delayed version of the comparator output is inverted.

9. The single slope ADC of claim 8 , wherein the first pulse generator includes a first pulse generator input and further comprises:

a delay element; and

an inverter connected in series with the delay element;

wherein the inverter and the delay element are connected between the first pulse generator input and the second logic gate input.

10. The single slope ADC of claim 6 , wherein the counter is a gray counter.

11. The single slope ADC of claim 6 , wherein the negative input of the second comparator is connected to the negative input of the first comparator.

12. An image detector comprising:

an array of detector unit cells including a first unit cell that includes a first unit cell output; and

a single slope analog to digital converter (ADC) coupled to the output first unit cell output, the ADC comprising:

a comparator having a positive input connected to the first unit cell output, a negative input and a comparator output;

a counter;

a latch connected to an output of the counter and that includes a trigger input; and

a pulse generator coupled to the comparator output that produces a pulse of a defined width each time a signal on the negative input transitions from a voltage level that is below a voltage level on the positive input to a voltage level that is above the voltage level on the positive input;

wherein the pulse generator includes a pulse generator output coupled to the trigger input and wherein the pulse generator includes a gate having first and second logic gate inputs, the first logic gate input being coupled to the comparator output and the second logic gate input being coupled to a delayed version of the comparator output.

13. The image detector of claim 12 , wherein the delayed version of the comparator output is inverted.

14. The image detector of claim 12 , wherein the pulse generator has a first pulse generator input and further comprises:

a delay element; and

an inverter connected in series with the delay element;

wherein the inverter and the delay element are connected between the first pulse generator input and the second logic gate input.

15. The image detector of claim 12 , wherein the counter is a gray counter.

16. The image detector of claim 12 , wherein the comparator comprises:

a first comparator having first positive and negative inputs and a first comparator output;

a second comparator having second positive and negative inputs and a second comparator output;

wherein the second negative input is connected to the first negative input.