Semiconductor device performing proximity sensing
View Patent ↗A semiconductor device includes a signal conversion circuit configured to convert a sensing current provided from a sensing element into a sensing voltage; an analog-to-digital converter (ADC) configured to convert the sensing voltage to a digital value; and a driving circuit configured to drive a light emitting element, wherein the ADC generates a digital value corresponding to proximity to an object by performing a primary operation comparing a ramp signal varying with time and the sensing voltage while the light emitting element is not driven and a secondary operation comparing the ramp signal and the sensing voltage while the light emitting element is driven.
1. A semiconductor device comprising:
a bias generating circuit configured to sample a bias voltage according to a reset signal; and
a current source configured to provide a bias current according to the bias voltage,
wherein the bias generating circuit includes:
a PMOS transistor having a gate and a drain coupled in common; and
a bias sampling capacitor; and
a switch configured to couple a gate of the PMOS transistor and the bias sampling capacitor according to the reset signal.
2. A semiconductor device comprising:
a signal conversion circuit configured to convert a sensing current provided from a sensing element into a sensing voltage;
an analog-to-digital converter (ADC) configured to convert the sensing voltage to a digital value; and
a driving circuit configured to drive a light emitting element,
wherein the ADC generates a digital value corresponding to proximity to an object by performing a primary operation comparing a ramp signal varying with time and the sensing voltage while the light emitting element is not driven and a secondary operation comparing the ramp signal and the sensing voltage while the light emitting element is driven,
wherein the ADC includes:
a ramp signal generating device configured to generate the ramp signal;
a comparator configured to compare the ramp signal and the sensing voltage;
a counter configured to count a clock signal during the primary operation and the secondary operation;
a first latch configured to store counter value of the counter in the primary operation;
a second latch configured to store counter value of the counter in the secondary operation; and
a signal processing circuit configured to generate the digital value according to outputs from the first latch and the second latch, and,
wherein the ramp signal generating device includes:
a bias generating circuit;
a current control circuit having a current source whose current is adjusted according to the bias generating circuit and generating an output current whose value is increasing or decreasing by a predetermined amount according to time; and
an output resistor generating a ramp signal at an output node corresponding to the output current.
3. The semiconductor device of claim 2 , wherein the signal conversion circuit includes:
an operational amplifier;
a bias circuit providing a bias voltage to a positive input terminal of the operational amplifier; and
a feedback resistor coupled between a negative input terminal of the operational amplifier where the sensing current is provided and an output terminal of the operational amplifier.
4. The semiconductor device of claim 2 , wherein the current control circuit includes a first current control circuit having a plurality of first unit current control circuits, wherein each of the plurality of first unit current control circuits provides a first unit current as the output current, and the first current control circuit adjusts the output current by the first unit current.
5. The semiconductor device of claim 4 , wherein the current control circuit includes a second current control circuit having a plurality of second unit current control circuits, wherein each of the plurality of second unit current control circuits provides a second unit current as the output current, and the second current control circuit adjusts the output current by the second unit current.
6. The semiconductor device of claim 5 , wherein the first current control circuit and the second current control circuit provides respective maximum current at initial stages of the primary operation and the secondary operation.
7. The semiconductor device of claim 6 , wherein the current control circuit further includes an initial current circuit configured to provide an initial current at the initial stages of the primary operation and the secondary operation as the output current.
8. The semiconductor device of claim 4 , wherein the first unit current control circuit includes a current source controlled by a bias voltage,
wherein the bias generating circuit provides a predetermined voltage as the bias voltage during a reset operation performed before the primary operation and the secondary operation.
9. The semiconductor device of claim 8 , wherein the bias generating circuit includes a bias sampling capacitor storing the bias voltage during the reset operation.
10. The semiconductor device of claim 2 , wherein the current control circuit further generates a second output current varying in opposite direction to the output current with time,
wherein the ramp signal generating circuit further includes a second output resistor generating a second output voltage corresponding to the second output current at a second output node.
11. The semiconductor device of claim 10 , wherein the ramp signal generating circuit further includes a capacitor coupled in parallel to the output resistor.
12. The semiconductor device of claim 10 , wherein the ramp signal generating circuit further includes a unit gain amplifier coupled between the output node and the second output node.
13. The semiconductor device of claim 2 , wherein the ADC further includes a coupling capacitor providing the ramp signal and the sensing voltage to the comparator.
14. The semiconductor device of claim 13 , wherein the comparator is a differential amplifier including a positive input terminal and a negative input terminal, and performs an auto-zero operation before the primary operation and the secondary operation where the positive input terminal and the negative input terminal are commonly coupled to a common mode voltage.