Semiconductor package
The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing method of a package-on-package (PoP) semiconductor structure, including forming a first redistribution layer (RDL) on a polymer-based layer of a carrier, defining an active portion and a dummy portion of the first RDL, placing a semiconductor die over the dummy portion of the first RDL, a back side of the semiconductor die facing the first RDL, forming a second RDL over a front side of the semiconductor die, the front side having at least one contact pad, and attaching a semiconductor package at the back side of the semiconductor die.
1. A semiconductor structure, comprising:
a first redistribution layer (RDL) having a plurality of pads;
a semiconductor die over the first RDL, at least one contact pad being positioned on a front side of the semiconductor die;
an adhesive layer at a back side of the semiconductor die and filling a gap between the plurality of pads, the back side being opposite to the front side; and
a through package via (TPV) electrically connecting the front side and the first RDL.
2. The semiconductor structure of claim 1 , wherein the plurality of pads of the first RDL further comprises a dummy portion electrically isolated from any component of the semiconductor structure.
3. The semiconductor structure of claim 1 , wherein the plurality of pads of the first RDL further comprises an active portion electrically coupled to a through package via.
4. The semiconductor structure of claim 1 , further comprising a molding compound encapsulating the first RDL and the semiconductor die.
5. The semiconductor structure of claim 4 , further comprising a through package via in the molding compound, electrically connected to the first RDL.
6. The semiconductor structure of claim 1 , further comprising a second RDL over the front side of the semiconductor die, electrically connected to the at least one contact pad.
7. The semiconductor structure of claim 6 , further comprising a through package via electrically connecting the first RDL and the second RDL.
8. A package-on-package (PoP) structure, comprising:
a polymer-based layer, having a first side and a second side opposite to the first side;
a first redistribution layer (RDL) at the first side of the polymer-based layer; and
a first semiconductor die attaching to the first RDL,
a carrier at the second side of the polymer-based layer,
wherein the first RDL is electrically coupled to the carrier via a conductive plug passing through the polymer-based layer.
9. The PoP structure of claim 8 , wherein the first RDL further comprises an active portion and a dummy portion.
10. The PoP structure of claim 9 , wherein the active portion is electrically connected to the conductive plug passing through the polymer-based layer.
11. The PoP structure of claim 9 , further comprising a second RDL electrically coupled to the active portion of the first RDL.
12. The PoP structure of claim 8 , further comprising a second semiconductor die connected to the carrier, the second semiconductor die electrically coupling to the first semiconductor die through a carrier via passing through the carrier.
13. The PoP structure of claim 8 , further comprising an underfill between the polymer-based layer and the carrier.
14. The PoP structure of claim 8 , further comprising a seed layer between the first RDL and the polymer-based layer.
15. A semiconductor package, comprising:
a polymer-based layer;
a first redistribution layer (RDL) over the polymer-based layer, the first RDL is comprising a dummy portion attached to a first side of the polymer-based layer; and
a semiconductor die over the dummy portion,
wherein a projection boundary of the dummy portion is greater than a projection boundary of the semiconductor die from the top view perspective.
16. The semiconductor package of claim 15 , further comprising a second RDL over a front side of the semiconductor die, the front side having at least one contact pad.
17. The semiconductor package of claim 16 , further comprising a ball grid array over the second RDL.
18. The semiconductor package of claim 15 , wherein the first RDL further comprises an active portion attached to the first side of the polymer-based layer.
19. The semiconductor package of claim 15 , wherein the dummy portion comprises a plurality of pads under the semiconductor die.
20. The semiconductor package of claim 19 , wherein the plurality of pads are arranged to be symmetric to a geometric center.