Fin-FET devices and fabrication methods thereof

1. A method for fabricating a Fin-FET device, comprising:

forming a plurality of fin structures, an isolation layer, and an interlayer dielectric layer, on a substrate, wherein the substrate includes an N-type metal-oxide-semiconductor (NMOS) region, the plurality of fin structures extend in the NMOS region, the isolation layer covers a portion of sidewall surfaces of the plurality of fin structures and has a top surface lower than top surfaces of the plurality of fin structures, the interlayer dielectric layer covers the isolation layer;

forming a first opening in the interlayer dielectric layer, wherein the first opening is formed across the plurality of fin structures in the NMOS region and exposes a portion of top and sidewall surfaces of the plurality of fin structures in the NMOS region, and a corner region is adjacent to a joint between a bottom surface and a sidewall surface of the first opening;

forming a high-k dielectric layer on the bottom surface and the sidewall surface of the first opening, wherein the high-k dielectric layer covers the portion of the top and the sidewall surfaces of the plurality of fin structures exposed in the first opening;

forming a barrier layer on the high-k dielectric layer in the first opening;

forming an N-type work function layer on the barrier layer, wherein the N-type work function layer is made of an N-type work function material containing aluminum ions;

performing an annealing process on the N-type work function layer such that the N-type work function layer has a thickened portion at the corner region and a portion of the N-type work function layer at the corner region includes diffused aluminum ions; and

forming a metal layer on the N-type work function layer to fill up the first opening.

2. The method for fabricating the Fin-FET device according to claim 1 , wherein a portion of each fin structure formed above a top surface of the isolation layer further includes:

a fin-structure bottom region; and

a fin-structure top region situated above the fin-structure bottom region, wherein:

the annealing process leads to a decreased thickness for a portion of the N-type work function layer formed on the fin-structure bottom region.

3. The method for fabricating the Fin-FET device according to claim 2 , wherein:

prior to performing the annealing process, the thickness of the portion of the N-type work function layer formed on the fin-structure bottom region is in a range of approximately 33 Å to 88 Å; and

after performing the back flow annealing process, the thickness of the portion of the N-type work function layer formed on the fin-structure bottom region is in a range of approximately 30 Å to 80 Å.

4. The method for fabricating the Fin-FET device according to claim 1 , wherein:

the top surface of the isolation layer formed between neighboring fin structures is curved in.

5. The method for fabricating the Fin-FET device according to claim 1 , wherein process parameters used in the annealing process include:

an annealing temperature in a range of approximately 100° C. to 300° C.; and

an annealing time in a range of approximately 10 min to 20 min.

6. The method for fabricating the Fin-FET device according to claim 1 , wherein:

the N-type work function layer is made of one of TiAl, TiAlC, TiAlN, and AlN.

7. The method for fabricating the Fin-FET device according to claim 1 , wherein:

the barrier layer is made of one of TiN and TaN.

8. The method for fabricating the Fin-FET device according to claim 1 , wherein:

prior to performing the annealing process, a thickness of the barrier layer is in a range of approximately 10 Å to 20 Å.

9. The method for fabricating the Fin-FET device according to claim 1 , wherein:

a width of the bottom region of the plurality of fin structures formed above the top surface of the isolation layer is larger than a width of the top region of the plurality of fin structures.

10. The method for fabricating the Fin-FET device according to claim 1 , wherein:

the substrate also includes a P-type metal-oxide-semiconductor (PMOS) region,

the plurality of fin structures extend in the PMOS region; and

a second opening is formed in the interlayer dielectric layer, wherein the second opening is formed across the plurality of fin structures in the PMOS region and exposes a portion of top and sidewall surfaces of the plurality of fin structures in the PMOS region.

11. The method for fabricating the Fin-FET device according to claim 10 , wherein:

a high-k dielectric layer is formed on a bottom surface and a sidewall surface of the second opening;

a P-type work function layer is formed on the high-k dielectric layer in the second opening; and

a metal layer is formed on the P-type work function layer and fills up the second opening.

12. The method for fabricating the Fin-FET device according to claim 11 , wherein forming the high-k dielectric layer, the barrier layer and the P-type work function layer includes:

forming the high-k dielectric layer on the bottom surface and the sidewall surface of the first opening, wherein the high-k dielectric layer is also simultaneously formed on the bottom surface and the sidewall surface of the second opening;

forming a first work function layer on the high-k dielectric layer in both the first opening and the second opening;

removing a portion of the first work function layer formed in the first opening to expose the high-k dielectric layer in the first opening; and

forming a second work function layer on the high-k dielectric layer in the first opening and the first work function layer in the second opening, wherein:

a portion of the second work function layer formed in the first opening serves as the barrier layer; and

a portion of the first work function layer together with a portion of the second work function layer formed in the second opening serve as the P-type work function layer.

13. The method for fabricating the Fin-FET device according to claim 11 , wherein:

the first work function layer is made of one of TiN and TaN; and

the second work function layer is made of one of TiN and TaN.

14. The method for fabricating the Fin-FET device according to claim 1 , prior to forming the metal layer, further including:

forming a cap layer on the N-type work function layer; and

the cap layer is made of one of TiN and TaN.

15. The method for fabricating the Fin-FET device according to claim 1 , wherein the high-k dielectric layer is made of one of HfO 2 , HfSiO, HfSiON, HfTaO, HfSiO, HfZrO, ZrO 2 , and Al 2 O 3 .

16. The method for fabricating the Fin-FET device according to claim 1 , wherein the metal layer is made of one of Cu, Al, and W.

17. The method for fabricating the Fin-FET device according to claim 1 , wherein the high-k dielectric layer, the barrier layer, and the N-type work function layer are also formed on a portion of the top surface of the interlayer dielectric layer prior to forming the metal layer; accordingly, forming the metal layer includes:

forming a metal film on the N-type work function layer to fill up the first opening, wherein a top surface of the metal film is higher than the top surface of the interlayer dielectric layer; and

removing the portion of the metal film, the high-k dielectric layer, the barrier layer, and the N-type work function layer formed above the top surface of the interlayer dielectric layer.