Semiconductor device
A semiconductor device includes an insulating layer on a substrate, a first channel pattern on the insulating layer and contacting the insulating layer, second channel patterns on the first channel pattern and being horizontally spaced apart from each other, a gate pattern on the insulating layer and surrounding the second channel patterns, and a source/drain pattern between the second channel patterns.
1. A semiconductor device, comprising:
an insulating layer on a substrate;
a first channel pattern on the insulating layer, the first channel pattern contacting the insulating layer;
second channel patterns on the first channel pattern, the second channel patterns being horizontally spaced apart from each other;
a gate pattern on the insulating layer, the gate pattern surrounding the second channel patterns; and
a source/drain pattern between the second channel patterns.
2. The device according to claim 1 , wherein the gate pattern comprises:
a conductive pattern on a top surface and sidewalls of the first channel pattern and on top surfaces, bottom surfaces and sidewalls of the second channel patterns; and
a gate insulating layer between the conductive pattern and the first and second channel patterns.
3. The device according to claim 2 , wherein the gate insulating layer extends on a top surface of the insulating layer.
4. The device according to claim 1 , further comprising:
spacers between the gate pattern and the source/drain pattern, the spacers being vertically spaced apart from each other with a respective one of the second channel patterns interposed therebetween.
5. The device according to claim 4 , wherein the spacers include,
a first spacer that is selectively between the first channel pattern and lowermost ones of the second channel patterns and between the second channel patterns, and
a second spacer on uppermost ones of the second channel patterns, the second spacer extending in a direction.
6. The device according to claim 1 , wherein the first channel pattern is interposed between the insulating layer and the source/drain pattern.
7. The device according to claim 6 , wherein the first channel pattern includes a first part under the source/drain pattern and a second part under the second channel patterns,
wherein a thickness of the first part is less than a thickness of the second part.
8. The device according to claim 6 , wherein the first channel pattern includes a first part under the source/drain pattern and a second part under the second channel patterns,
wherein a thickness of the first part is substantially equal to a thickness of the second part.
9. The device according to claim 1 , wherein the source/drain pattern contacts the first channel pattern and the second channel patterns.
10. A semiconductor device, comprising:
an insulating layer on a substrate;
channel patterns on the insulating layer and being vertically spaced apart from each other, the channel patterns including a first channel pattern corresponding to a lowermost one of the channel patterns relative to the insulating layer, and a second channel pattern on the first channel pattern, the first channel pattern contacting the insulating layer;
a gate pattern on the insulating layer, the gate pattern surrounding the second channel pattern; and
a source/drain pattern at a side of the gate pattern,
wherein a bottom surface of the first channel pattern is positioned at substantially the same level as a bottom surface of the source/drain pattern relative to a top surface of the substrate.
11. The device according to claim 10 , wherein the source/drain pattern contacts the insulating layer.
12. The device according to claim 10 , further comprising:
spacers on opposite sidewalls of the gate pattern,
wherein a sum of a thickness of the gate pattern and thicknesses of the spacers is substantially equal to a width of each of the first and second channel patterns.
13. The device according to claim 10 , wherein a width of the first channel pattern is substantially equal to a width of the second channel pattern.
14. The device according to claim 10 , wherein the gate pattern comprises:
a conductive pattern; and
a gate insulating layer between the conductive pattern and the first and second channel patterns,
wherein the conductive pattern is disposed on a top surface and sidewalls of the first channel pattern and on a top surface, a bottom surface and sidewalls of the second channel pattern.
15. A semiconductor device comprising:
a first channel pattern contacting an insulating layer;
a gate pattern on the first channel pattern;
a source/drain pattern at a side of the gate pattern; and
second channel patterns with gate-all-around structures on the second channel pattern,
wherein the source/drain pattern is on the first channel pattern such that the source/drain pattern does not contact the insulating layer.
16. The semiconductor device of claim 15 , wherein the source/drain pattern contacts the insulating layer.
17. The semiconductor device of claim 15 , wherein the gate pattern includes,
a conductive pattern; and
a gate insulating layer between the conductive pattern and the channel patterns.
18. The semiconductor device of claim 15 , wherein the first channel pattern includes a first part under the source/drain pattern and a second part under the gate pattern,
wherein a thickness of the first part is less than a thickness of the second part.