Controllers including separate input-output circuits for mapping table and buffer memory, solid state drives including the controllers, and computing systems including the solid state drives
Solid state drives may include a controller, a mapping table and a buffer memory. The controller provides a logical address of associated data through a first input-output unit at a first speed and provides the associated data through a second input-output unit at a second speed. The controller may be connected to the first input-output unit and the second input-output unit. The mapping table may be connected to the controller through the first input-output unit. The buffer memory may be connected to the controller through the second input-output unit. The first input-output unit may be physically separated from the second input-output unit. The first speed may be different from the second speed.
1. A solid state drive comprising:
a controller configured to provide a logical address of associated data through a first input-output circuit at a first speed and configured to provide the associated data through a second input-output circuit at a second speed, the controller being connected to the first input-output circuit and the second input-output circuit, the first input-output circuit being physically separated from the second input-output circuit and the second speed being greater than the first speed;
a first volatile memory comprising a mapping table, the mapping table being connected to the controller through the first input-output circuit and configured to map the logical address of the associated data that is provided through the first input-output circuit to a physical address of the associated data; and
a second volatile memory comprising a buffer memory, the buffer memory being connected to the controller through the second input-output circuit and configured to buffer the associated data that is provided through the second input-output circuit,
wherein a storage capacity of the mapping table is greater than a storage capacity of the buffer memory,
wherein the first input-output circuit includes a first number of first input-output lines,
wherein the second input-output circuit includes a second number of second input-output lines, and the first number is different from the second number, and
wherein a second parasitic capacitance of the second input-output circuit connected to the second volatile memory is different than a first parasitic capacitance of the first input-output circuit connected to the first volatile memory.
2. The solid state drive of claim 1 , wherein the controller is configured to receive an input signal including the logical address of the associated data and the associated data, and
wherein the controller includes a selection circuit that is configured to separate the associated data from the logical address of the associated data.
3. The solid state drive of claim 2 , wherein the selection circuit is configured to provide the logical address of the associated data to the mapping table through the first input-output circuit.
4. The solid state drive of claim 2 , wherein the selection circuit is configured to provide the associated data to the buffer memory through the second input-output circuit.
5. The solid state drive of claim 1 , wherein the second number of second input-output lines is greater than the first number.
6. The solid state drive of claim 1 , wherein the first volatile memory comprises a first Dynamic Random Access Memory (DRAM), and the second volatile memory comprises a second DRAM that is physically separated from the first DRAM.
7. The solid state drive of claim 6 , wherein a ratio of the storage capacity of the mapping table to the storage capacity of the buffer memory is 9:1.
8. The solid state drive of claim 1 further comprising a non-volatile storage memory, wherein the non-volatile storage memory is configured to receive the associated data and the physical address of the associated data from the controller.
9. The solid state drive of claim 8 , wherein the buffer memory is configured to receive the associated data only from the controller through the second input-output circuit.
10. A solid state drive comprising:
a controller configured to transmit a logical address of associated data at a first speed and the associated data through an input-output circuit at a second speed that is greater than the first speed; and
a memory device including a first Dynamic Random Access Memory (DRAM) comprising a mapping table and a second DRAM comprising a buffer memory,
wherein the first DRAM is physically separated from the second DRAM,
wherein a storage capacity of the mapping table is greater than a storage capacity of the buffer memory,
wherein the mapping table is configured to receive the logical address of the associated data from the controller through the input-output circuit and configured to map the logical address of the associated data to a physical address of the associated data,
wherein the buffer memory is configured to receive the associated data from the controller through the input-output circuit and configured to buffer the associated data,
wherein the input-output circuit comprises a first input-output circuit and a second input output circuit, and
wherein a second parasitic capacitance of the second input-output circuit is different than a first parasitic capacitance of the first input-output circuit.
11. The solid state drive of claim 10 , wherein the second input-output circuit is physically separated from the first input-output circuit, and
wherein the mapping table is configured to receive the logical address of the associated data from the controller through the first input-output circuit, and the buffer memory is configured to receive the associated data from the controller through the second input-output circuit.
12. The solid state drive of claim 11 , wherein the first input-output circuit comprises a first number of input-output lines, and the second input-output circuit comprises a second number of input-output lines, and
wherein the second number is greater than the first number.
13. The solid state drive of claim 10 , wherein the second input-output circuit is physically separated from the first input-output circuit, and
wherein the first input-output circuit is directly connected to the controller and the first DRAM, and the second input-output circuit is directly connected to the controller and the second DRAM.
14. The solid state drive of claim 10 further comprising a non-volatile storage memory, wherein the non-volatile storage memory is configured to receive the associated data and the physical address of the associated data from the controller.
15. The solid state drive of claim 14 , wherein the buffer memory is configured to receive the associated data only from the controller through the input-output circuit.
16. The solid state drive of claim 10 , wherein a ratio of the storage capacity of the mapping table to the storage capacity of the buffer memory is 9:1.