IP Library Granted Patent US 10,095,653
Granted Patent B2
US 10,095,653 · App. 15/089,531 · Granted Oct 9, 2018

Apparatuses, systems, and methods for accurately measuring packet propagation delays through USB retimers

Inventor: Steven B. McGowan (Portland, OR)
Assignee: Intel Corporation
G06F13/4291G06F13/1673G06F13/4295H04L9/3297G06F13/36H04L25/0298
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Quick Facts
Patent No.
US 10,095,653
App. No.
15/089,531
Granted
Oct 9, 2018
Kind
B2
Abstract

Methods and apparatuses relating to measuring propagation delays through USB retimers are described. In one embodiment, a retimer apparatus includes a receiver to receive a data block and a timestamp for the data block from an upstream device, a buffer to store the data block and the timestamp for transmittal, a controller to modify the timestamp to generate a modified timestamp that includes a time from a receipt of a first portion of the data block in the buffer until a transmittal of the first portion of the data block from the buffer, and a transmitter to transmit the data block and the modified timestamp to a downstream device.

Claims (40)

1. A retimer apparatus comprising:

a receiver to receive a data block and a timestamp for the data block from an upstream device;

a buffer to store the data block and the timestamp for transmittal;

a controller to modify the timestamp to generate a modified timestamp that includes a time from a receipt of a first portion of the data block in the buffer until a transmittal of the first portion of the data block from the buffer; and

a transmitter to transmit the data block and the modified timestamp to a downstream device wherein the controller associates a second timestamp in a clock domain of the transmitter with the timestamp from the upstream device.

2. The retimer apparatus of claim 1 , wherein the time from receipt of the first portion of the data block until the transmittal of the first portion of the data block is tracked in a single clock domain.

3. The retimer apparatus of claim 1 , wherein the modified timestamp is a modified Isochronous Timestamp Packet.

4. The retimer apparatus of claim 1 , wherein the controller is to further modify the timestamp to generate the modified timestamp that includes a Link Delay Measurement for a first link between the upstream device and the retimer apparatus.

5. The retimer apparatus of claim 1 , wherein the second timestamp represents the receipt of the first portion of the data block in the clock domain of the transmitter.

6. The retimer apparatus of claim 1 , wherein the second timestamp passes through the buffer with the data block and the timestamp for the data block.

7. The retimer apparatus of claim 1 , further comprising a counter to track the time from receipt of the first portion of the data block until the transmittal of the first portion of the data block.

8. A method comprising:

receiving a data block and a timestamp for the data block from an upstream device with a receiver of a retimer apparatus;

associating a second timestamp in a clock domain of a transmitter of the retimer apparatus with the timestamp from the upstream device;

storing the data block and the timestamp for transmittal in a buffer of the retimer apparatus;

modifying the timestamp to generate a modified timestamp including a time from a receipt of a first portion of the data block in the buffer until a transmittal of the first portion of the data block from the buffer; and

transmitting the data block and the modified timestamp to a downstream device with the transmitter of the retimer apparatus.

9. The method of claim 8 , wherein the time from receipt of the first portion of the data block until the transmittal of the first portion of the data block is tracked in a single clock domain.

10. The method of claim 8 , wherein the modified timestamp is a modified Isochronous Timestamp Packet.

11. The method of claim 8 , comprising further modifying the timestamp to generate the modified timestamp including a Link Delay Measurement for a first link between the upstream device and the retimer apparatus.

12. The method of claim 8 , wherein the second timestamp represents the receipt of the first portion of the data block in the clock domain of the transmitter.

13. The method of claim 8 , further comprising passing the second timestamp through the buffer with the data block and the timestamp for the data block.

14. The method of claim 8 , further comprising tracking the time from receipt of the first portion of the data block until the transmittal of the first portion of the data block with a counter.

15. An apparatus comprising:

a hardware processor;

a host; and

a retimer apparatus comprising:

a receiver to receive a data block and a timestamp for the data block from the host;

a buffer to store the data block and the timestamp for transmittal;

a controller to modify the timestamp to generate a modified timestamp that includes a time from a receipt of a first portion of the data block in the buffer until a transmittal of the first portion of the data block from the buffer; and

a transmitter to transmit the data block and the modified timestamp to a downstream device wherein the controller associates a second timestamp in a clock domain of the transmitter with the timestamp from the host.

16. The apparatus of claim 15 , wherein the time from receipt of the first portion of the data block until the transmittal of the first portion of the data block is tracked in a single clock domain.

17. The apparatus of claim 15 , wherein the modified timestamp is a modified Isochronous Timestamp Packet.

18. The apparatus of claim 15 , wherein the controller is to further modify the timestamp to generate the modified timestamp that includes a Link Delay Measurement for a first link between the host and the retimer apparatus.

19. The apparatus of claim 15 , wherein the second timestamp represents the receipt of the first portion of the data block in the clock domain of the transmitter.

20. The apparatus of claim 15 , wherein the second timestamp passes through the buffer with the data block and the timestamp for the data block.

21. The apparatus of claim 15 , further comprising a counter to track the time from receipt of the first portion of the data block until the transmittal of the first portion of the data block.

22. The retimer apparatus of claim 1 , wherein the receiver comprises a synchronizer to convert the second timestamp from the clock domain of the transmitter to a clock domain of the receiver.

23. The method of claim 8 , further comprising converting the second timestamp from the clock domain of the transmitter to a clock domain of the receiver with a synchronizer of the receiver.

24. The apparatus of claim 15 , wherein the retimer apparatus comprises a synchronizer to convert the second timestamp from the clock domain of the transmitter to a clock domain of the receiver.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2018
From: MCGOWAN, STEVEN B.
To: INTEL CORPORATION
Reel/Frame 046652/0156 →
Continuity (1)
Related Publication 20170286359A1 · Oct 5, 2017