Secure access to peripheral devices over a bus
An apparatus includes an interface and a processor. The interface is configured for communicating over a bus. The processor is configured to disrupt on the bus a transaction in which a bus-master device attempts to access a peripheral device without authorization, by forcing one or more dummy values on at least one line of the bus in parallel to at least a part of the transaction.
1. An apparatus, comprising:
an interface for communicating over a bus connected to a peripheral device; and
a processor, which is connected to the bus as an additional slave device in parallel with the peripheral device, and which is configured to disrupt on the bus a transaction in which a bus-master device attempts to access the peripheral device without authorization, by superimposing one or more dummy values on a line of the bus in addition to one or more corresponding values asserted on the line as part of the transaction.
2. The apparatus according to claim 1 , wherein the processor is configured to superimpose the dummy values on a data line of the bus, so as to disrupt transfer of respective data values that are sent to or received from the peripheral device on the data line.
3. The apparatus according to claim 1 , wherein the processor is configured to superimpose the dummy values on a clock line of the bus, so as to disrupt a clock signal used in the transaction.
4. The apparatus according to claim 1 , wherein the processor is configured to superimpose the dummy values on a chip-select line of the bus, so as to disrupt selection of the peripheral device by the bus-master device.
5. The apparatus according to claim 1 , wherein the bus comprises an open-drain or open-collector bus having a default logical value, and wherein the processor is configured to superimpose the dummy values by writing an opposite of the default logical value on the line of the bus.
6. The apparatus according to claim 1 , wherein, by superimposing the dummy values, the processor is configured to override the corresponding values that are written on the line by the bus-master device or by the peripheral device.
7. The apparatus according to claim 6 , wherein the processor is configured to override the corresponding values written by the bus-master device or by the peripheral device, by driving the line with a drive strength that is stronger than the drive strength of the bus-master device or the peripheral device.
8. The apparatus according to claim 6 , and comprising at least one resistor, which is inserted in the line and is configured to attenuate the corresponding values written by the bus-master device or by the peripheral device, relative to the dummy values written by the processor.
9. The apparatus according to claim 1 , wherein the processor is configured to superimpose the dummy values using only existing lines of the bus that are used for communicating between the bus-master device and the peripheral device.
10. The apparatus according to claim 1 , wherein the processor is configured to detect the transaction to be disrupted, by monitoring the bus.
11. The apparatus according to claim 1 , wherein the processor is configured to detect the transaction to be disrupted, by communicating with the bus-master device over an auxiliary interface that is external to the bus.
12. The apparatus according to claim 1 , wherein the processor is configured to superimpose the dummy values indefinitely, until the apparatus is reset.
13. The apparatus according to claim 1 , wherein the processor is configured to superimpose the dummy values for a finite time period after detecting the transaction.
14. The apparatus according to claim 1 , wherein the processor is configured to resume normal operation of the bus following disruption of the transaction.
15. A system, comprising:
a peripheral device that is accessible to one or more bus-master devices over a bus; and
a security device, which is connected to the bus as an additional slave device in parallel with the peripheral device, and which is configured to disrupt on the bus a transaction in which a bus-master device attempts to access the peripheral device without authorization, by superimposing one or more dummy values on a line of the bus in addition to one or more corresponding values asserted on the line as part of the transaction.
16. A method, comprising:
using a security device, which is coupled to a bus as an additional slave device in parallel with a peripheral device, deciding to disrupt a transaction in which a bus-master device attempts to access the peripheral device without authorization; and
disrupting the transaction by superimposing one or more dummy values on a line of the bus in addition to one or more corresponding values asserted on the line as part of the transaction.
17. The method according to claim 16 , wherein the bus comprises an open-drain or open-collector bus having a default logical value, and wherein superimposing the dummy values comprises writing an opposite of the default logical value on the line of the bus.
18. The method according to claim 16 , wherein superimposing the dummy values comprises overriding the corresponding values that are written on the line by the bus-master device or by the peripheral device.
19. The method according to claim 16 , wherein superimposing the dummy values is performed using only existing lines of the bus that are used for communicating between the bus-master device and the peripheral device.
20. The method according to claim 16 , and comprising detecting the transaction to be disrupted, by monitoring the bus.
21. The method according to claim 16 , and comprising detecting the transaction to be disrupted, by communicating with the bus-master device over an auxiliary interface that is external to the bus.
22. The method according to claim 16 , and comprising resuming normal operation of the bus following disruption of the transaction.