Power switch circuit for non-volatile memory
A non-volatile memory includes a power switch circuit and a non-volatile cell array. The power switch circuit includes a first transistor, a second transistor and a current source. A first source/drain terminal and a gate terminal of the first transistor receive a first supply voltage and a second supply voltage, respectively. A second source/drain terminal and a body terminal of the first transistor are connected with a node z. A first source/drain terminal and a gate terminal of the second transistor receive the second supply voltage and the first supply voltage, respectively. A second source/drain terminal and a body terminal of the second transistor are connected with the node z. The current source is connected between a bias voltage and the node z. A power terminal of the non-volatile cell is connected with the node z for receiving an output signal.
1. A non-volatile memory, comprising:
a non-volatile cell array having a power terminal; and
a power switch circuit, including:
a first transistor, wherein a first source/drain terminal of the first transistor receives a first supply voltage, a second source/drain terminal of the first transistor is connected with a node z, a gate terminal of the first transistor receives a second supply voltage, a body terminal of the first transistor is connected with the node z, and an output signal is outputted from the node z;
a second transistor, wherein a first source/drain terminal of the second transistor receives the second supply voltage, a second source/drain terminal of the second transistor is connected with the node z, a gate terminal of the second transistor receives the first supply voltage, and a body terminal of the second transistor is connected with the node z; and
a current source connected between a bias voltage and the node z,
wherein the power terminal of the non-volatile cell array is connected with the node z for receiving the output signal; and
wherein if the first supply voltage is lower than the second supply voltage, the first supply voltage is selected as the output signal, wherein if the first supply voltage is higher than the second supply voltage, the second supply voltage is selected as the output signal, wherein if the first supply voltage is equal to the second supply voltage, the bias voltage is selected as the output signal.
2. The non-volatile memory as claimed in claim 1 , wherein the bias voltage is equal to the first supply voltage, or the bias voltage is equal to the second supply voltage.
3. The non-volatile memory as claimed in claim 1 , wherein the first transistor and the second transistor are n-type transistors, and the current source is a weak current source.