Semiconductor apparatus, system, and method of manufacturing semiconductor apparatus
There is provided an image capturing apparatus including a pixel circuit that generates a pixel signal based on an electric charge generated by photoelectric conversion and a logic circuit that outputs a signal based on the pixel signal. The image capturing apparatus includes a first contact plug connected to a source or a drain of a first transistor constituting the pixel circuit and a second contact plug connected to a source or a drain of a second transistor constituting the logic circuit. A diameter of the first contact plug is smaller than a diameter of the second contact plug.
1. A semiconductor apparatus comprising:
a first transistor;
a first contact plug connected to a source or a drain of the first transistor;
a second transistor;
a second contact plug connected to a source or a drain of the second transistor; and
a third contact plug connected to a gate of the second transistor,
wherein the first transistor constitutes a pixel circuit configured to generate a pixel signal based on an electric charge generated by photoelectric conversion,
wherein the second transistor constitutes a logic circuit configured to output a signal based on the pixel signal,
wherein a diameter of the first contact plug is smaller than a diameter of the second contact plug, and
wherein the diameter of the first contact plug is smaller than a diameter of the third contact plug.
2. The semiconductor apparatus according to claim 1 ,
wherein the diameter of the second contact plug is not less than 1.30 times the diameter of the first contact plug.
3. The semiconductor apparatus according to claim 1 ,
wherein the diameter of the second contact plug is not less than 1.50 times and not more than 2.00 times the diameter of the first contact plug.
4. The semiconductor apparatus according to claim 1 ,
wherein the diameter of the first contact plug is not less than 50 nm and is less than 200 nm, and the diameter of the second contact plug is not less than 200 nm and not more than 300 nm.
5. The semiconductor apparatus according to claim 1 ,
wherein a diameter of a fourth contact plug connected to a gate of the first transistor is less than 1.30 times the diameter of the first contact plug.
6. The semiconductor apparatus according to claim 1 ,
wherein a fourth contact plug connected to a gate of the first transistor is positioned over a channel region of the first transistor.
7. The semiconductor apparatus according to claim 1 ,
wherein a plurality of contact plugs including the second contact plug are connected to the drain of the second transistor.
8. The semiconductor apparatus according to claim 1 ,
wherein the first transistor and the second transistor are insulated-gate field-effect transistors, and a gate insulating film of the first transistor is thicker than a gate insulating film of the second transistor.
9. The semiconductor apparatus according to claim 1 ,
wherein a contact plug connected to a third transistor that is connected to the pixel circuit and constitutes a current source, has a diameter that is larger than the diameter of the first contact plug.
10. The semiconductor apparatus according to claim 1 ,
wherein a second semiconductor region is provided between a first semiconductor region that constitutes the drain of the first transistor and the first contact plug,
wherein a silicide region is provided between a third semiconductor region that constitutes the drain of the second transistor and the second contact plug, and
wherein an impurity concentration of the second semiconductor region is higher than an impurity concentration of the first semiconductor region.
11. The semiconductor apparatus according to claim 1 ,
wherein the first contact plug includes a first conductive portion disposed in a first contact hole having a side and a bottom, and a first barrier metal portion including a side portion interposed between the side of the first contact hole and the first conductive portion, and a bottom portion interposed between the bottom of the first contact hole and the first conductive portion of the first contact plug,
wherein the second contact plug includes a second conductive portion disposed in a second contact hole having a side and a bottom, and a second barrier metal portion including a side portion interposed between the side of the second contact hole and the second conductive portion, and a bottom portion interposed between the bottom of the second contact hole and the second conductive portion, and
wherein a ratio of a thickness of the bottom portion of the second barrier metal portion to a thickness of the side portion of the second barrier metal portion is larger than a ratio of a thickness of the bottom portion of the first barrier metal portion to a thickness of the side portion of the first barrier metal portion.
12. The semiconductor apparatus according to claim 1 ,
wherein the drain of the first transistor has a single drain structure, and the drain of the second transistor has a lightly doped drain structure.
13. The semiconductor apparatus according to claim 1 ,
wherein the first transistor is a transfer transistor configured to transfer the electric charge.
14. The semiconductor apparatus according to claim 1 ,
wherein the second transistor is included in a complementary metal oxide semiconductor circuit.
15. A system comprising:
the semiconductor apparatus according to claim 1 ; and
a signal processing device configured to process a signal output from the semiconductor apparatus.
16. A semiconductor apparatus comprising:
a first transistor;
a first contact plug connected to the first transistor;
a second transistor; and
a second contact plug connected to the second transistor,
wherein the first contact plug includes a first conductive portion disposed in a first contact hole having a side and a bottom, and a first barrier metal portion including a side portion interposed between the side of the first contact hole and the first conductive portion, and a bottom portion interposed between the bottom of the first contact hole and the first conductive portion of the first contact plug,
wherein the second contact plug includes a second conductive portion disposed in a second contact hole having a side and a bottom, and a second barrier metal portion including a side portion interposed between the side of the second contact hole and the second conductive portion, and a bottom portion interposed between the bottom of the second contact hole and the second conductive portion,
wherein a ratio of a thickness of the bottom portion of the first barrier metal portion to a thickness of the side portion of the first barrier metal portion is smaller than a ratio of a thickness of the bottom portion of the second barrier metal portion to a thickness of the side portion of the second barrier metal portion, and
wherein the thickness of the bottom portion of the second barrier metal portion is larger than the thickness of the bottom portion of the first barrier metal portion.
17. The semiconductor apparatus according to claim 16 ,
wherein the first transistor and the second transistor are insulated-gate field-effect transistors, and a thickness of a gate insulating film of the first transistor is different from a thickness of a gate insulating film of the second transistor.
18. The semiconductor apparatus according to claim 16 ,
wherein a second semiconductor region is provided between a first semiconductor region that constitutes a drain of the first transistor and the first contact plug,
wherein a silicide region is provided between a third semiconductor region that constitutes a drain of the second transistor and the second contact plug, and
wherein an impurity concentration of the second semiconductor region is higher than an impurity concentration of the first semiconductor region.
19. A system comprising:
the semiconductor apparatus according to claim 16 ; and
a signal processing device configured to process a signal output from the semiconductor apparatus.