Monolithically integrated resistive memory using integrated-circuit foundry compatible processes

1. A memory device, comprising:

a substrate including one or more complementary metal-oxide semiconductor devices;

a first insulator layer formed on the substrate; and

a monolithic stack comprising multiple layers fabricated as part of a monolithic process over the first insulator layer, wherein the multiple layers comprise a first metal layer, a second insulator layer, and a second metal layer, wherein a resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices, the resistive memory device structure is implemented as a pillar device, and wherein the first metal layer is electrically connected by way of an electrical conductor material to at least a portion of the second metal layer.

2. The memory device of claim 1 , wherein the monolithic stack is formed within foundry compatible process restrictions, and a defined distance between the first metal layer and the second metal layer is substantially similar to a distance between the second metal layer and a third metal layer.

3. The memory device of claim 1 , wherein the resistive memory device structure is fabricated at a temperature of 450 degrees Celsius or lower.

4. The memory device of claim 1 , wherein the pillar device comprises a pillar formed on the first metal layer and a collar, wherein the collar comprises two layers of material that contact the second metal layer at a first surface.

5. The memory device of claim 4 , wherein a first layer of material of the two layers of material comprises a first side that contacts the pillar and a second side that contacts a second surface of a second layer of material of the two layers of material, wherein a first surface of the second layer of material contacts the first surface of the second metal layer, and wherein the first surface and the second surface of the second layer of material are located on opposite sides of the second layer of material.

6. The memory device of claim 1 , wherein the pillar device comprises a base comprising conducting material and a first layer over the base comprising switching material and a second layer over the first layer comprising another conducting material.

7. The memory device of claim 6 , wherein at least one of:

the base comprises a first thickness and the first layer over the base or the second layer over the first layer comprises a second thickness different from the first thickness; or

a cross section of the base has a first perimeter and a second cross section of the first layer over the base or of the second layer over the first layer has a second perimeter, and wherein the first perimeter is of smaller length than the second perimeter.

8. The memory device of claim 1 , wherein the pillar device comprises a first cylinder or a first approximation of a cylinder that includes resistive switching material, and a second cylinder or a second approximation of a cylinder that includes an active material.

9. The memory device of claim 1 wherein the pillar device includes a base comprising SiGe, a resistive switching material comprising SiOx, and an active material comprising a silver material, an aluminum material, or a copper material.

10. A method of fabricating a memory device, comprising:

fabricating a pair of metal layers having a defined distance there between; and

fabricating a monolithic stack that comprises multiple layers, wherein the fabricating is performed within a thermal budget of a substrate of the memory device and with a stack height less than or equal to the defined distance, the fabricating comprises:

providing the substrate comprising one or more complementary metal-oxide semiconductor devices;

fabricating a first insulator layer over the substrate;

fabricating a first metal layer of the pair of metal layers over the first insulator layer;

fabricating an interlayer dielectric material layer over the first metal layer;

fabricating a resistive memory device structure within the interlayer dielectric material layer comprising forming a pillar device;

fabricating a second metal layer of the pair of metal layers over the resistive memory device structure; and

forming an electrical contact between the first metal layer and at least a portion of the second metal layer.

11. The method of claim 10 , the method being a foundry compatible process and further comprising forming a third metal layer a distance from the second metal layer approximately equal to the defined distance.

12. The method of claim 10 , wherein the fabricating the monolithic stack comprises fabricating the monolithic stack at a temperature of about 450 degrees Celsius or lower.

13. The method of claim 12 , wherein the fabricating the monolithic stack comprises fabricating the monolithic stack at a temperature between about 400 and 450 degrees Celsius.

14. The method of claim 12 , wherein the fabricating the monolithic stack comprises fabricating the monolithic stack at a temperature between about 350 and 400 degrees Celsius.

15. The method of claim 12 , wherein the fabricating the monolithic stack comprises fabricating the monolithic stack at a temperature between about 300 and 350 degrees Celsius.

16. The method of claim 10 , wherein forming the pillar device further comprises depositing, patterning and etching a stack of material layers, comprising a conductive base layer, a resistive-switching layer over the conductive base layer, and a second conductive layer over the resistive-switching layer, and further comprising forming the resistive-switching layer or the second conductive layer to have a larger cross-section area than a second cross-section area of the conductive base layer.

17. A memory cell, comprising:

a substrate comprising one or more complementary metal-oxide semiconductor devices;

a first insulator layer formed on the substrate; and

a monolithic stack comprising multiple layers fabricated as part of a monolithic process over the first insulator layer, wherein the multiple layers comprise a first metal layer formed on a top surface of the substrate, a first conductive layer formed on the first metal layer, a second insulator layer, and a second metal layer, wherein a resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices, and wherein an electrical conductive material connects the first metal layer to at least a portion of the second metal layer.

18. The memory cell of claim 17 , wherein the resistive memory device structure is fabricated at a temperature of about 450 degrees Celsius or lower.

19. The memory cell of claim 17 , wherein the resistive memory device structure comprises a pillar device that comprises a base material formed on the first metal layer and a collar formed on the base material, wherein the collar comprises two or more layers of material, and contacts the second metal layer at a first surface of the collar.

20. The memory cell of claim 19 , wherein a first layer of the collar comprises a first side that contacts the pillar and a second side that contacts a second surface of a second layer of the collar, and further wherein the first surface and the second surface are located on opposite sides of the second layer of the collar.