Multi-level page data structure
Methods, systems, and computer program products for receiving a memory allocation request; comparing a memory size corresponding to the memory allocation request to a memory size threshold; allocating a memory page that has a size larger than the memory size threshold, the memory page having a page entry in a page management data structure; and allocating a portion of the memory page, the portion of the memory page corresponding to a sub-page of the memory page.
1. A method for accessing memory of a computer, the method comprising:
receiving a memory allocation request;
comparing a memory size corresponding to the memory allocation request to a memory size threshold;
allocating a memory page that has a size larger than the memory size threshold, the memory page having a page entry in a page management data structure;
allocating a portion of the memory page, the portion of the memory page corresponding to a sub-page of the memory page;
setting a parameter in the page entry, the parameter indicating that the memory page includes one or more sub-pages; and
creating a sub-page entry corresponding to the sub-page within the allocated portion of the memory page.
2. The method of claim 1 , wherein the sub-page entry comprises the following parameters: an address space corresponding to the sub-page; an index into the address space; and one or more flags corresponding to the sub-page.
3. The method of claim 1 , wherein the memory page has a size of two megabytes and the sub-page has a size of four kilobytes.
4. The method of claim 1 , wherein the page entry has a struct data type.
5. The method of claim 1 , wherein the page entry includes a parameter that identifies a page frame number corresponding to the memory page.
6. The method of claim 1 , wherein the page management data structure is a page array.
7. The method of claim 1 , wherein a virtual address of the memory page includes an alignment indicator, the alignment indicator including a plurality of bits that are all set to zero.
8. The method of claim 1 , wherein a virtual address of the sub-page includes an alignment indicator that includes one or more bits that are set to one.
9. The method of claim 1 , wherein the sub-page entry includes a parameter that identifies a page frame number corresponding to the sub-page.
10. The method of claim 1 , further comprising:
updating a lookup structure, wherein the lookup structure identifies a range of physical memory corresponding to the page management data structure.
11. A computer program product stored on a non-transitory computer-readable medium, the computer program product comprising machine readable instructions that when executed by a processor cause the processor to:
determine that a memory size corresponding to the memory allocation request is below a memory size threshold;
allocate a memory page, the memory page having a page entry in a page array;
allocate a sub-page of the memory page, the sub-page included within a range of physical memory allocated to the memory page; and
set a parameter in the page entry to indicate that the memory page includes one or more sub-pages; and
create a sub page entry corresponding to the sub-page within the range of physical memory allocated to the memory page.
12. The medium of claim 11 , the processor further to: create the sub-page entry at a start offset of the sub-page, wherein the sub-page entry includes at least the following parameters: an address space corresponding to the sub-page; an index into the address space; and one or more flags corresponding to the sub-page.
13. The medium of claim 12 , wherein the page entry includes a page frame number corresponding to the memory page, and wherein the sub-page entry includes a page frame number corresponding to the sub-page.
14. The medium of claim 11 , wherein the memory page has a size of two megabytes and the sub-page has a size of four kilobytes.
15. The medium of claim 11 , wherein a virtual address of the memory page includes a plurality of alignment bits that are all set to zero, wherein a virtual address of the sub-page includes at least one alignment bit that is set to one.
16. A system for managing memory pages, the system comprising:
a processor and a memory, the memory including a sub-page that is stored within a memory page;
the memory including a page array that includes a page entry corresponding to a memory page;
the page entry including a parameter that indicates that the memory page is split into one or more sub-pages;
the processor to create a sub-page entry in a sub-page of the one or more sub-pages, the sub-page entry including at least the following parameters: an address space corresponding to the sub-page; an index into the address space; and one or more flags corresponding to the sub-page.
17. The system of claim 16 , wherein the page entry identifies a page frame number of the memory page, and wherein the sub-page entry identifies a page frame number of the sub-page.
18. The system of claim 16 , wherein the memory page has a size of two megabytes and the sub-page has a size of four kilobytes.
19. The system of claim 16 , wherein a virtual address of the memory page includes a plurality of alignment bits that are all set to zero, wherein a virtual address of the sub-page includes at least one alignment bit that is set to one.