Thin film transistor substrate for flat panel display
The present disclosure relates to a thin film transistor substrate for flat panel display including an organic light emitting diode display. The present disclosure provides a device comprising: a substrate; a scan line extending in a first direction on the substrate; a buffer layer on the scan line; a semiconductor layer extending in a second direction and crossing the scan line on the buffer layer; a gate insulating layer on the semiconductor layer; a gate electrode connected to the scan line, and extending in the first direction and crossing the semiconductor layer on the gate insulating layer; an intermediate insulating layer on the gate electrode; a data line crossing the scan line on the intermediate insulating layer; a source electrode branching from the data line and contacting a first side of the semiconductor layer; and a drain electrode facing the source electrode and contacting a second side of the semiconductor layer.
1. A device, comprising:
a substrate;
a scan line extending in a first direction on the substrate;
a buffer layer on the scan line;
a semiconductor layer extending in a second direction and crossing the scan line on the buffer layer;
a gate insulating layer on the semiconductor layer;
a gate electrode connected to the scan line, the gate electrode extending in the first direction and crossing the semiconductor layer on the gate insulating layer;
an intermediate insulating layer on the gate electrode;
a data line crossing the scan line on the intermediate insulating layer;
a source electrode branching from the data line and contacting a first side of the semiconductor layer; and
a drain electrode facing the source electrode and contacting a second side of the semiconductor layer,
wherein the scan line includes a bottle neck portion at an area where the scan line crosses the semiconductor layer.
2. The device according to the claim 1 , wherein the gate electrode overlaps the scan line, and
the gate electrode is connected to the scan line via a contact hole penetrating the buffer layer and the gate insulating layer.
3. The device according to the claim 1 , wherein the bottle neck portion is overlapped with the gate electrode, and
wherein the scan line has a narrower width in the bottle neck portion than in other portions of the scan line.
4. The device according to the claim 3 , wherein the gate electrode and the bottle neck portion have a same width and completely overlap each other.
5. The device according to the claim 1 , wherein the scan line has a first side and a second side and a first width between the first side and the second side,
wherein the bottle neck portion has a second width that is less than the first width, and is disposed adjacent to the first side of the scan line, and
wherein the gate electrode is disposed adjacent to the second side of the scan line and is not overlapped with the bottle neck portion.
6. The device according to the claim 5 , wherein the gate electrode and the bottle neck portion are spaced apart from each other with a predetermined distance.
7. The device according to the claim 1 , further comprising:
a driving current line crossing the scan line on the intermediate insulating layer;
a driving thin film transistor connected between the drain electrode and the driving current line; and
an organic light emitting diode connected to the driving thin film transistor.
8. A device, comprising:
a substrate;
a scan line extending in a first direction on the substrate;
a semiconductor layer extending in a second direction that is transverse to the first direction, the semiconductor layer at least partially overlapping the scan line;
a gate electrode connected to the scan line, the gate electrode extending in the first direction and at least partially overlapping the semiconductor layer;
a data line extending in the second direction and crossing the scan line;
a source electrode that extends from the data line and contacts a first side region of the semiconductor layer; and
a drain electrode that contacts a second side region of the semiconductor layer that is opposite to the first side region,
wherein the scan line includes a bottle neck portion at an area where the scan line crosses over the semiconductor layer.
9. The device according to the claim 8 , wherein the bottle neck portion is overlapped with the gate electrode, and
wherein the scan line has a narrower width in the bottle neck portion than in other portions of the scan line.
10. The device according to the claim 9 , wherein the gate electrode and the bottle neck portion have a same width and completely overlap each other.
11. The device according to the claim 8 , wherein the scan line has a first side and a second side and a first width between the first side and the second side,
wherein the bottle neck portion has a second width that is less than the first width, and is disposed adjacent to the first side of the scan line, and
wherein the gate electrode is disposed adjacent to the second side of the scan line and is not overlapped with respect to the bottle neck portion.