IP Library › Granted Patent US 10,103,229
Granted Patent B2
US 10,103,229 · App. 15/291,297 · Granted Oct 16, 2018

Semiconductor device and method of manufacturing semiconductor device

Inventors: Yasuyuki Hoshi (Nagano, JP); Yuichi Harada (Nagano, JP); Takashi Shiigi (Nagano, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/1608H01L21/02529H01L21/76895H01L21/823807H01L23/535H01L24/26H01L27/092H01L29/0649H01L29/2003H01L29/36H01L29/66712H01L29/7805H01L29/8611
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Quick Facts
Patent No.
US 10,103,229
App. No.
15/291,297
Granted
Oct 16, 2018
Kind
B2
Abstract

A semiconductor device includes a wide-bandgap semiconductor substrate of a first conductivity type, a wide-bandgap semiconductor deposition layer of the first conductivity type, semiconductor regions of a second conductivity type, a wide-bandgap semiconductor layer of the second conductivity type, first regions of the first conductivity type, and second regions of the first conductivity type. The width w of a plating film formed on a source electrode of the semiconductor device is greater than or equal to 10 μm. Beneath the plating film, the wide-bandgap semiconductor layer is formed on the surface of one of the semiconductor regions of the second conductivity type.

Claims (37)

1. A semiconductor device, comprising:

a wide-bandgap semiconductor substrate of a first conductivity type made of a semiconductor having a wider bandgap than silicon;

a wide-bandgap semiconductor deposition layer of the first conductivity type that is deposited on a front surface of the wide-bandgap semiconductor substrate and that has a lower impurity concentration than the wide-bandgap semiconductor substrate;

a semiconductor region of a second conductivity type that is selectively formed in a surface layer of the wide-bandgap semiconductor deposition layer on a side opposite to the wide-bandgap semiconductor substrate;

a wide-bandgap semiconductor layer of the second conductivity type that is made of a semiconductor having a wider bandgap than silicon and that is formed on surfaces of the wide-bandgap semiconductor deposition layer and the semiconductor region of the second conductivity type;

a first region of the first conductivity type selectively formed in a portion of the wide-bandgap semiconductor layer that is above the deposition layer;

a second region of the first conductivity type that is selectively formed in the wide-bandgap semiconductor layer;

a gate electrode formed on a surface of a portion of the wide-bandgap semiconductor layer that is sandwiched between the second region of the first conductivity type and the first region of the first conductivity type;

a gate insulating film interposed between the gate electrode and the wide-bandgap semiconductor layer;

a source electrode that contacts the wide-bandgap semiconductor layer and the second region of the first conductivity type;

an interlayer insulating film that covers the gate electrode;

a drain electrode formed on a rear surface of the wide-bandgap semiconductor substrate;

a plating film selectively formed on the source electrode; and

a pin electrode that is connected to the plating film via solder,

wherein a width of the plating film in a direction parallel to the wide-bandgap semiconductor substrate is greater than or equal to 10 μm, and

wherein the second region of the first conductivity type and the first region of the first conductivity type are not formed in a portion of the wide-bandgap semiconductor layer facing the plating film.

2. The semiconductor device according to claim 1 ,

wherein the source electrode has a bump-shaped portion, and

wherein a difference in height, from the front surface of the wide-bandgap semiconductor substrate, of said bump-shaped portion is less than or equal to 2 μm.

3. The semiconductor device according to claim 1 , wherein the interlayer insulating film is covered by a nitride film.

4. The semiconductor device according to claim 1 , wherein the source electrode is selectively covered by a nitride film.

5. A method of manufacturing a semiconductor device, comprising:

forming, on a front surface of a wide-bandgap semiconductor substrate of a first conductivity type made of a semiconductor having a wider bandgap than silicon, a wide-bandgap semiconductor deposition layer of the first conductivity type that has a lower impurity concentration than the wide-bandgap semiconductor substrate;

selectively forming, in a surface layer of the wide-bandgap semiconductor deposition layer, a semiconductor region of a second conductivity type;

forming, on surfaces of the wide-bandgap semiconductor deposition layer, a wide-bandgap semiconductor layer of the second conductivity type that is made of a semiconductor having a wider bandgap than silicon;

selectively forming, in a portion of the wide-bandgap semiconductor layer that is above the deposition layer, a first region of the first conductivity type;

selectively forming a second region of the first conductivity type in the wide-bandgap semiconductor layer;

forming a gate electrode on a surface of a portion of the wide-bandgap semiconductor layer that is sandwiched between the second region of the first conductivity type and the first region of the first conductivity type,

forming a gate insulating film between the gate electrode and the wide-bandgap semiconductor layer;

forming a source electrode that contacts the wide-bandgap semiconductor layer and the second region of the first conductivity type;

forming an interlayer insulating film that covers the gate electrode;

forming a drain electrode on a rear surface of the wide-bandgap semiconductor substrate;

selectively forming a plating film on the source electrode; and

forming a pin electrode that is connected to the plating film via solder,

wherein in the step of forming the plating film, the plating film is formed having a width of greater than or equal to 10 μm in a direction parallel to the wide-bandgap semiconductor substrate,

wherein in the step of selectively forming the first region of the first conductivity type, the first region of the first conductivity type is not formed in a portion of the wide-bandgap semiconductor layer that faces the plating film, and

wherein in the step of selectively forming the second region of the first conductivity type, the second region of the first conductivity type is not formed in a portion of the wide-bandgap semiconductor layer that faces the plating film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2016
From: HOSHI, YASUYUKI; HARADA, YUICHI; SHIIGI, TAKASHI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 039996/0678 →
Priority Claims (1)
JP 2015-205336 · Oct 19, 2015 · national
Continuity (1)
Related Publication 20170110544A1 · Apr 20, 2017