Latency-optimized physical coding sublayer
A method for reducing latency in a networking application includes receiving data at a physical coding sublayer (PCS) from a media access control (MAC) sublayer, where the MAC sublayer utilizes a first clock domain operating at a first clock frequency. The method further includes performing one or more functions in the PCS on the data in the first clock domain. The method also includes transmitting the data on one or more physical medium attachment (PMA) lanes, where the one or more PMA lanes utilize a second clock domain operating at a second clock frequency, where the first clock frequency and the second clock frequency have a fixed ratio. The data is transmitted from the first clock domain to the second clock domain without buffering the data. The method also includes performing one or more functions in the PCS on the data in the second clock domain.
1. A method comprising:
receiving data at a physical coding sublayer (PCS) from a media access control (MAC) sublayer, wherein the MAC sublayer utilizes a first clock domain operating at a first clock frequency;
performing one or more functions in the PCS on the data in the first clock domain;
after performing one or more functions in the PCS, transmitting the data on one or more physical medium attachment (PMA) lanes coupled to the PCS, wherein the one or more PMA lanes utilize a second clock domain operating at a second clock frequency, wherein the first clock frequency and the second clock frequency have a fixed ratio, and wherein transmitting data from the first clock domain to the second clock domain comprises determining, based on the fixed ratio, a first portion of a received data block to transmit during a clock cycle and a second portion of the received data block to delay transmitting until a subsequent clock cycle; and
performing one or more functions in the PCS on the data in the second clock domain.
2. The method of claim 1 , wherein performing one or more functions on the data in the first clock domain comprises encoding and scrambling the data to create one or more 66-bit blocks.
3. The method of claim 1 , further comprising:
after performing one or more functions on the data in the second clock domain, transmitting the data to an asynchronous output first-in, first-out (FIFO) located in the first clock domain in the PCS.
4. The method of claim 1 , wherein performing one or more functions on the data in the first clock domain comprises inserting one or more alignment markers in the data.
5. The method of claim 4 , wherein performing one or more functions on the data in the second clock domain comprises removing one or more alignment markers in the data.
6. The method of claim 1 , further comprising transmitting data from a transmit side of the PCS to a receive side of the PCS via one or more PMA lanes.
7. The method of claim 6 , wherein the data is received from the one or more PMA lanes in one or more plesiochronous input FIFOs on the receive side of the PCS.
8. The method of claim 7 , wherein the data in a subset of the plesiochronous input FIFOs is synchronized to the data in one of the plesiochronous input FIFOs that is designated as a master.
9. The method of claim 1 , wherein performing one or more functions on the data in the second clock domain comprises deskewing the data.