Electronic apparatus and non-transitory computer readable medium for power consumption control of processors

1. An electronic apparatus, comprising:

a processor including a plurality of cores that divisionally execute each of a plurality of tasks;

a total task amount calculation circuit that calculates, for each of the cores, a total task amount as a total processing amount of the plurality of tasks to be executed;

a sleep shift processing circuit that causes a part of the plurality of cores to shift to a sleep mode based on the total task amount calculated for each of the cores;

a sleep recovery processing circuit that causes, when the one of the cores is in the sleep mode, the core in the sleep mode to recover from the sleep mode based on the total task amount;

a sleep shift check circuit that determines whether the total task amount of a specific core has fallen below a first threshold value; and

a sleep recovery check circuit that determines, when one of the cores is in the sleep mode, whether the total task amount of the cores not in the sleep mode exceeds a third threshold value,

wherein

the sleep shift processing circuit causes the cores whose total task amount has fallen below the first threshold value to shift to the sleep mode based on the determination by the sleep shift check circuit,

the sleep shift check circuit further determines whether the total task amount of the cores excluding the cores whose total task amount has fallen below the first threshold value exceeds a second threshold value,

the sleep shift processing circuit causes, when the total task amount of the cores excluding the cores whose total task amount has fallen below the first threshold value does not exceed the second threshold value based on the determination by the sleep shift check circuit, the cores whose total task amount has fallen below the first threshold value to shift to the sleep mode,

the sleep recovery processing circuit causes, when the total task amount of the cores not in the sleep mode exceeds the third threshold value based on the determination by the sleep recovery check circuit, the cores in the sleep mode to recover from the sleep mode,

the first threshold value is smaller than the second threshold value, and

the third threshold value is larger than the second threshold value.

2. The electronic apparatus according to claim 1 ,

wherein the sleep shift processing circuit hands over a task that the core, which has been shifted to the sleep mode, has been processing to the core excluding the core that has been shifted to the sleep mode.

3. The electronic apparatus according to claim 1 ,

wherein the sleep recovery processing circuit hands over a task that the core not in the sleep mode has been processing to the core that has been recovered from the sleep mode.

4. The electronic apparatus according to claim 1 ,

wherein, when the total task amounts of the plurality of cores have fallen below the first threshold value, the sleep shift processing circuit

causes a core having a smaller total task amount to sleep, and

hands over a task that the core, which has been shifted to the sleep mode, has been processing to the core excluding the core that has been shifted to the sleep mode.

5. The electronic apparatus according to claim 1 , further comprising

a sleep recovery check circuit that determines, when one of the cores is in the sleep mode, whether the total task amount of the core not in the sleep mode exceeds a third threshold value,

wherein the sleep recovery processing circuit causes, when the total task amount of the core not in the sleep mode exceeds the third threshold value based on the determination by the sleep recovery check circuit, the core in the sleep mode to recover from the sleep mode.

6. The electronic apparatus according to claim 5 ,

wherein, after the core is recovered from the sleep mode, the sleep recovery processing circuit

temporarily causes the core not in the sleep mode to continue processing of the task to be executed by the core that has been recovered from the sleep mode, and

thereafter hands over the task that has temporarily been continued by the core not in the sleep mode to the core that has been recovered from the sleep mode.

7. The electronic apparatus according to claim 1 , wherein

the plurality of cores have the same processing capacity,

the first threshold value is 20% the total task amount that the core is capable of processing within a certain time,

the second threshold value is 60% the total task amount that the core is capable of processing within the certain time, and

the third threshold value is 80% the total task amount that the core is capable of processing within the certain time.

8. The electronic apparatus according to claim 1 , wherein:

the sleep shift check circuit determines whether a new task has occurred; and

the sleep shift processing circuit hands over, when the total task amount of one of the cores exceeds the total task amount that can be processed within a certain time due to the occurrence of a new task while all the plurality of cores are processing tasks, an excessive portion of the processing amount of the new task to the other core.

9. The electronic apparatus according to claim 1 ,

wherein the processor including the plurality of cores is a plurality of symmetric-multiprocessing-type processors.

10. A non-transitory computer readable recording medium that records a power supply control program executable by a computer, the computer including a processor including a plurality of cores that divisionally execute each of a plurality of tasks, the power supply control program causing the computer to operate as:

a total task amount calculation circuit that

calculates, for each of the cores, a total task amount as a total processing amount of the plurality of tasks to be executed;

a sleep shift processing circuit that causes one of the plurality of cores to shift to a sleep mode based on the total task amount calculated for each of the cores;

a sleep shift processing circuit that causes, when the one of the cores is in the sleep mode, the core in the sleep mode to recover from the sleep mode based on the total task amount;

a sleep shift check circuit that determines whether the total task amount of a specific core has fallen below a first threshold value; and

a sleep recovery check circuit that determines, when one of the cores is in the sleep mode, whether the total task amount of the cores not in the sleep mode exceeds a third threshold value,

wherein

the sleep shift processing circuit causes the cores whose total task amount has fallen below the first threshold value to shift to the sleep mode based on the determination by the sleep shift check circuit,

the sleep shift check circuit further determines whether the total task amount of the cores excluding the cores whose total task amount has fallen below the first threshold value exceeds a second threshold value,

the sleep shift processing circuit causes, when the total task amount of the cores excluding the cores whose total task amount has fallen below the first threshold value does not exceed the second threshold value based on the determination by the sleep shift check circuit, the cores whose total task amount has fallen below the first threshold value to shift to the sleep mode,

the sleep recovery processing circuit causes, when the total task amount of the cores not in the sleep mode exceeds the third threshold value based on the determination by the sleep recovery check circuit, the cores in the sleep mode to recover from the sleep mode,

the first threshold value is smaller than the second threshold value, and

the third threshold value is larger than the second threshold value.