Composite carrier for warpage management
A composite carrier is disclosed for warpage management as a temporary carrier in semiconductor process. Warpage is reduced for a product, semi-product, or build-up layer processed on the temporary composite carrier which is peeled off the temporary carrier in a later step. The composite carrier comprises a top substrate and a bottom substrate, an adhesive layer is configured in between the top substrate and a bottom substrate. One of the embodiments discloses the top substrate of the composite carrier having a lower CTE and the bottom substrate of the composite carrier having a higher CTE.
1. A composite carrier for warpage management, comprising:
a top substrate having opposing top and bottom surfaces, and a side surface located between the top and bottom surfaces of the top substrate;
a bottom substrate below the top substrate, the bottom substrate having opposing top and bottom surfaces, and a side surface located between the top and bottom surfaces of the bottom substrate;
an adhesive layer between the top substrate and the bottom substrate, the adhesive layer bonding the top substrate to the bottom substrate, the adhesive layer having opposing top and bottom surfaces, and a side surface located between the top and bottom surfaces of the adhesive layer; and
a polymer, wrapping around the side surface of each of the top substrate, the bottom substrate and the adhesive layer,
wherein the polymer has a first portion flush with the top surface of the top substrate, and a second portion flush with the bottom surface of the bottom substrate, the top substrate has a first chamfer extending between the top surface and the side surface of the top substrate, the bottom substrate has a second chamfer extending between the bottom surface and the side surface of the bottom substrate,
wherein the polymer comprises an inner surface adjacent to and covering the first chamfer, the side surface of the top substrate, the side surface of the adhesive layer, the side surface of the bottom substrate, and the second chamfer,
wherein the top surface of the top substrate includes an area for semiconductor processing thereon,
the composite carrier further comprises a multi-layer structure arranged on, and detachable from, the top surface of the top substrate, in the area for semiconductor processing,
wherein the multi-layer structure comprises a plurality of build-up layers,
wherein each of the build-up layers comprises a plurality of metal layers embedded in a dielectric layer, and
wherein adjacent build-up layers are electrically connected,
one of the top substrate and the bottom substrate is made of a material selected from the group consisting of:
silicon (Si) having a CTE around 3 ppm,
cemented carbide having a CTE around 5.5 ppm,
aluminum (Al) having a CTE around 7.2 ppm,
titanium (Ti) having a CTE around 8.6 ppm,
copper clad laminate (CCL) having a CTE around 1˜17 ppm,
aluminum oxide (Al 2 O 3 ) having a CTE around 7 ppm,
aluminum nitride (AlN) having a CTE around 5 ppm, and
zirconia (ZrO 2 ) having a CTE around 10.5 ppm, and
the other of the top substrate and the bottom substrate is made of a material selected from the group consisting of:
silicon (Si) having a CTE around 3 ppm,
cemented carbide having a CTE around 5.5 ppm,
aluminum (Al) having a CTE around 7.2 ppm,
titanium (Ti) having a CTE around 8.6 ppm,
glass having a CTE around 0˜10 ppm,
copper clad laminate (CCL) having a CTE around 1˜17 ppm,
stainless steel having a CTE around 10˜18.0 ppm,
Alloy 42 having a CTE around 4.8 ppm,
aluminum oxide (Al 2 O 3 ) having a CTE around 7 ppm,
aluminum nitride (AlN) having a CTE around 5 ppm, and
zirconia (ZrO 2 ) having a CTE around 10.5 ppm.
2. The composite carrier for warpage management as claimed in claim 1 , wherein
a thickness of the top substrate equals to a thickness of the bottom substrate.
3. The composite carrier for warpage management as claimed in claim 1 , wherein
a thickness of the top substrate is thinner than a thickness of the bottom substrate.
4. The composite carrier for warpage management as claimed in claim 1 , wherein
a thickness of the top substrate is thicker than a thickness of the bottom substrate.
5. The composite carrier for warpage management as claimed in claim 1 , wherein
one of the top substrate and the bottom substrate has a CTE around 1˜4 ppm; and the other one has a CTE around 4.5˜18 ppm.
6. The composite carrier for warpage management as claimed in claim 1 , wherein
the one of the top substrate and the bottom substrate is made of
silicon (Si) having a CTE around 3 ppm, and
the other substrate is made of a material selected from the group consisting of:
Alloy 42 having a CTE around 4.8 ppm,
aluminum nitride (AlN) having a CTE around 5 ppm,
cemented carbide having a CTE around 5.5 ppm,
aluminum (Al) having a CTE around 7.2 ppm,
aluminum oxide (Al 2 O 3 ) having a CTE around 7 ppm,
titanium (Ti) having a CTE around 8.6 ppm,
zirconia (ZrO 2 ) having a CTE around 10.5 ppm,
glass having a CTE around 0˜10 ppm, and
stainless steel having a CTE around 10˜18.0 ppm.
7. The composite carrier for warpage management as claimed in claim 6 , wherein
a thickness of the top substrate equals to a thickness of the bottom substrate.
8. The composite carrier for warpage management as claimed in claim 6 , wherein
a thickness of the top substrate is thinner than a thickness of the bottom substrate.
9. The composite carrier for warpage management as claimed in claim 6 , wherein
a thickness of the top substrate is thicker than a thickness of the bottom substrate.
10. The composite carrier for warpage management as claimed in claim 1 , wherein layers in the multi-layer structure have, in combination, a CTE higher than the top substrate.
11. The composite carrier for warpage management as claimed in claim 10 , wherein the bottom substrate has a CTE higher than the top substrate.
12. A composite carrier for warpage management, comprising:
a top substrate having a top surface and a first chamfered edge connected to the top surface, the top surface of the top substrate including an area for semiconductor processing;
a bottom substrate below the top substrate, the bottom substrate comprising a bottom surface and a second chamfered edge connected to the bottom surface;
an adhesive layer between the top substrate and the bottom substrate, the adhesive layer bonding the top substrate to the bottom substrate;
a polymer, comprising a first portion and a second portion respectively flush with the top surface of the top substrate and the bottom surface of the bottom substrate, and the polymer wrapping around the first chamfered edge of the top substrate, a lateral surface of the adhesive layer and the second chamfered edge of the bottom substrate; and
a multi-layer structure arranged on, and detachable from, the top surface of the top substrate, in the area for semiconductor processing,
wherein
layers in the multi-layer structure have, in combination, a coefficient of thermal expansion (CTE) higher than the top substrate,
the bottom substrate has a CTE higher than the top substrate,
the multi-layer structure comprises a build-up layer including a plurality of metal layers embedded in a dielectric layer, and
the top substrate is made of a material selected from the group consisting of:
silicon (Si) having a CTE around 3 ppm,
cemented carbide having a CTE around 5.5 ppm,
aluminum (Al) having a CTE around 7.2 ppm,
titanium (Ti) having a CTE around 8.6 ppm,
glass having a CTE around 0˜10 ppm,
copper clad laminate (CCL) having a CTE around 1˜17 ppm,
Aluminum oxide (Al 2 O 3 ) having a CTE around 7 ppm,
aluminum nitride (AlN) having a CTE around 5 ppm, and
zirconia (ZrO 2 ) having a CTE around 10.5 ppm.
13. The composite carrier for warpage management as claimed in claim 12 , wherein the adhesive layer is in direct contact with both the top substrate and the bottom substrate, and bonds the top substrate to the bottom substrate, and
a thickness of the adhesive layer is less than a thickness of each of the top substrate and the bottom substrate.
14. The composite carrier for warpage management as claimed in claim 13 , wherein the top substrate and the bottom substrate are glass substrates.