Transistor structure including a scandium gallium nitride back-barrier layer

1. A transistor comprising:

a substrate;

a buffer layer disposed on the substrate;

a back-barrier layer on the buffer layer, the back-barrier layer including scandium gallium nitride;

a channel layer disposed on the back-barrier layer; and

a barrier layer disposed on the channel layer, the barrier layer including at least one of aluminum gallium nitride, indium aluminum nitride, indium gallium aluminum nitride, scandium aluminum nitride, scandium gallium aluminum nitride, or indium gallium boron aluminum nitride.

2. The transistor of claim 1 , wherein the back-barrier layer includes scandium gallium nitride according to Sc x Ga 1-x N; and

wherein x is in a range between 0.01 and 0.40.

3. The transistor of claim 2 , wherein x is about 0.05; and

wherein a thickness of the back-barrier layer is in a range between 2.5 nm and 50 nm.

4. The transistor of claim 2 , wherein x is about 0.1; and

wherein a thickness of the back-barrier layer is in a range between 2.5 nm and 50 nm.

5. The transistor of claim 2 , wherein x is about 0.15; and

wherein a thickness of the back-barrier layer is in a range between 2.5 nm and 50 nm.

6. The transistor of claim 2 , wherein x is about 0.2; and

wherein a thickness of the back-barrier layer is in a range between 2.5 nm and 50 nm.

7. The transistor of claim 2 , wherein x is about 0.25; and

wherein a thickness of the back-barrier layer is in a range between 2.5 nm and 50 nm.

8. The transistor of claim 2 , wherein x is about 0.3; and

wherein a thickness of the back-barrier layer is in a range between 2.5 nm and 50 nm.

9. The transistor of claim 2 , wherein x is about 0.35; and

wherein the thickness of the back-barrier layer is in a range between 2.5 nm and 50 nm.

10. The transistor of claim 1 , wherein the barrier layer includes aluminum gallium nitride according to Al y Ga 1-y N; and

wherein y is in a range between 0.10 and 1.0.

11. The transistor of claim 10 , wherein y is about 0.23.

12. The transistor of claim 1 , further comprising:

a nucleation layer disposed between the substrate and the buffer layer; and

a spacer layer disposed between the channel layer and the barrier layer.

13. The transistor of claim 12 , wherein the substrate is silicon carbide, the nucleation layer is aluminum nitride, the channel layer is gallium nitride, and the spacer layer is aluminum nitride.

14. The transistor of claim 1 , further comprising:

a cap layer disposed on the barrier layer;

a drain contact coupled with the cap layer;

a source contact coupled with the cap layer; and

a gate contact coupled with the cap layer.

15. A method comprising:

forming a buffer layer on a substrate;

forming a back-barrier layer on the buffer layer, the back-barrier layer including scandium gallium nitride;

forming a channel layer on the back-barrier layer, the channel layer including gallium nitride; and

forming a barrier layer on the channel layer, the barrier layer including at least one of aluminum gallium nitride, indium aluminum nitride, indium gallium aluminum nitride, scandium aluminum nitride, scandium aluminum gallium nitride, or indium gallium boron aluminum nitride.

16. The method of claim 15 , further comprising:

forming an aluminum nitride spacer layer between the channel layer and the barrier layer.

17. The method of claim 15 , wherein the back-barrier layer includes scandium gallium nitride according to Sc x Ga 1-x N;

wherein x is in a range between 0.01 and 0.40; and

wherein a thickness of the back-barrier layer is in a range between 2.5 nm and 50 nm.

18. The method of claim 15 , wherein the barrier layer includes aluminum gallium nitride according to Al y Ga 1-y N; and

wherein y is in a range between 0.10 and 1.0.

19. The method of claim 18 , wherein the barrier layer includes aluminum gallium nitride according to Al y Ga 1-y N; and

wherein y is about 0.23.

20. The method of claim 15 , further comprising:

forming a nucleation layer between the substrate and the buffer layer; and

forming a cap layer on the barrier layer.

21. The method of claim 20 , further comprising:

forming a drain contact coupled with the cap layer;

forming a source contact coupled with the cap layer; and

forming a gate contact coupled with the cap layer.