IP Library › Granted Patent US 10,110,246
Granted Patent B1
US 10,110,246 · App. 15/732,173 · Granted Oct 23, 2018

Δ-Σ methods for frequency deviation measurement of know nominal frequency value

Inventor: Djuro G. Zrilic (Santa Fe, NM)
Assignee: Djuro G. Zrilic
H03M3/30
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Quick Facts
Patent No.
US 10,110,246
App. No.
15/732,173
Granted
Oct 23, 2018
Kind
B1
Abstract

Disclosed are three methods for precise measurement of frequency deviation of known nominal frequency. Delta adder method (DA), comprising of delta-sigma modulator, delta-adder, delay line, low-pass filter, and zero crossing detector. The second method (DA+RE), comprising of delta-sigma modulator, circuit for squaring delta-sigma bit-stream, delta-adder, low-pass filter, and zero-crossing detector. The third method comprises of reference delta-sigma modulator for synchronization of two or more dislocated frequency sources of known nominal frequency.

Claims (22)

1. A digital programable frequency meter for low frequencies with known nominal values, the frequency meter circuit comprising:

a first or higher order Δ-Σ modulator for producing bit-stream Xn;

a delay line to produce 90° shifted signal Xd;

a delta adder (DA) for addition of orthogonal bit-streams Xn and Xd, and produce signal A;

a low-pass filter (LPF) to receive digital signal A, and produce analog signal s(t);

a comparator C (zero-crossing detector) compares signal s(t) with a ground (zero voltage) to produce digital output C;

a positive edge of digital signal C is detected to reset a counter, which counts a number of a clock pulses between positive edges of the digital signal C;

a Count-to-Frequency converter, with display, serves for numerical display of a frequency deviation of an input signal x(t).

2. A digital programable frequency meter for low frequencies with known nominal values, the frequency meter circuit comprising:

a first or higher order Δ-Σ modulator for producing bit-stream Xn;

a rectifying encoder (RE) circuit to produce square signal of Rn;

a delay line to produce orthogonal signal Rd;

a delta adder DA for addition of orthogonal bit-streams Rn and Rd, and produce signal B;

a low-pass filter to receive digital signal B, and produce analog signal s(t);

a comparator (a zero-crossing detector) C compares signal s(t) with a ground (zero voltage) to produce digital output C;

a positive edge of digital signal C is detected to reset a counter, which counts a number of a clock pulses between positive edges of the digital signal C;

a Count-to-Frequency converter, with display, serves for numerical display of a frequency deviation of an input signal x(t).

3. A digital programmable frequency synchronization difference-meter, comprising:

a two (or more) identical first or higher order Δ-Σ modulators, converting input signals x 1 ( t ) and x 2 ( t ) of unstable frequency;

a reference Δ-Σ modulator; of a stable clock frequency, and a stable frequency of reference signal x r (t);

a two (or more) DA circuits (or DA+RE circuits) for producing bit-streams C 1 , Cr, and C 2 of a corresponding bit-stream frequencies F 1 , Fr, and F 2 ;

a two (or more) digital comparators for producing a difference signal between a reference bit-stream of a stable frequency Fr, and a bit-stream of an unstable frequency F 1 (signal D 1 ) or the reference bit-stream of a stable frequency Fr, and a bit-stream of an unstable frequency F 2 (signal D 2 ).

Cited By (2)
US 12,431,913 US 12,551,155