Integrated main memory and coprocessor with low latency
System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission. Paired I/O ports tied to unique global on-chip SD allow multiple external processors to slave chip and its resources independently and autonomously without scheduling between the external processors.
1. An integrated circuit (IC) comprising:
an input interface for receiving an external command and optional external data;
a main memory (MM) coupled to the input interface, the MM comprising:
a plurality of memory cells configured to store data;
a memory controller (MC) configured to execute an access command to one or more of the plurality of memory cells;
a coprocessor (CP) coupled to the input interface and the MM, the coprocessor comprising:
a processing engine (PE) coupled to the MM, wherein the processing engine is configured to execute a command for a subroutine call on data without requiring an interrupt;
an output interface for transmitting data, the output interface coupled to the MM and the PE;
a local data memory coupled to the PE;
a plurality of registers coupled to the PE; and wherein:
the local data memory and the plurality of registers are partitioned into a plurality of multi-threaded processing domains; and
data stored in the local data memory and in the plurality of registers is located in a partition of the local data memory and a partition of the plurality of registers, respectively, that matches a multi-threaded processing domain of the data.
2. The IC of claim 1 wherein:
the IC does not require an on-chip cache memory to temporarily store cached data from an external memory chip upon which cached data the PE executes an operation.
3. The IC of claim 1 wherein:
the CP is configured to fetch data upon which the PE executes an operation;
the data fetched by the CP is stored solely on the IC; and
the data fetched by the CP is not cached on-chip from an external main memory.
4. The IC of claim 1 wherein:
the execution of the access command to the MM and the execution of subroutine calls by the PE are performed concurrently and independently.
5. The IC of claim 1 wherein:
the coprocessor is not required to process the access command prior to the MC executing the access command.
6. The IC of claim 1 wherein:
the CP is configured to execute external commands for an EXACT MATCH, a LONGEST PREFIX MATCH (LPM), and a SEARCH operation on data in the MM; and
the MM is configured to execute external commands or internal commands generated on-chip for a READ, a WRITE, and a READ/MODIFY/WRITE (RMW) operation on data with the MM.
7. The IC of claim 1 wherein:
the CP is configured to execute instructions from an instruction memory for at least one function selected from a group of functions consisting of: hash, mask-plus-count (MPC), set-assign-compare (SAC), and error detection and correction (EDC).
8. The IC of claim 1 wherein:
the input interface is coupled to the MM and to the PE in parallel in order to communicate the external command to the MM and to the PE in parallel.
9. The IC of claim 1 wherein:
the CP is configured to execute a plurality of CMDs for network functions as requested by a packet forwarding engine (PFE) host; and
the plurality of network function CMDs is a subset of a full set of commands required of the PFE for processing network packets.
10. The IC of claim 1 wherein:
the PE is configured to execute a plurality of instructions;
the instructions comprise neither an INTERRUPT nor a CACHE CONTROL instruction.
11. The IC of claim 10 wherein:
an input buffer memory is configured to receive a plurality of commands from an external source according to an input sequence for a given scheduling domain; and
an output buffer memory is configured to output a plurality of results in an output sequence for the given scheduling domain; and
the input sequence for the given scheduling domain is the same as the output sequence for the given scheduling domain; and
the input sequence and the output sequence are a first-in-first-out (FIFO) sequence.
12. The IC of claim 1 wherein:
the input interface comprises a plurality of input ports;
the output interface comprises a plurality of output ports; and
each output port is slaved to one unique input port to form an input/output port pair.
13. The IC of claim 12 , wherein:
a first input port is configured to receive a command of a first type;
a second input port is configured to receive a command of a second type; and wherein:
a first command is received on a first input port;
a second command is received on a second input port; and
the first command and the second command are received concurrently;
the first and second commands are of different types;
the first command is received on the first input port from a first host;
the second command is received on the second input port from a second host; and
the first host and the second host are separate ICs.
14. The IC of claim 1 wherein:
the IC is configured to implement a plurality of multi-threaded domains;
the input interface and the output interface are configured for a first type of multi-threaded domain;
the coprocessor is configured for a second type of multi-threaded domain; and
at least two multi-threaded domains of the plurality of multi-threaded domains are independent from each other.
15. The IC of claim 1 further comprising:
a local data memory (LDM) coupled to the PE; and wherein:
the LDM has a memory capacity that is smaller that a memory capacity of the MM; and
a memory access speed by the PE to the LDM is faster than a memory access speed by the PE to the MM.
16. The IC of claim 1 further comprising:
a memory scheduler (MS) coupled to the MM and the PE; and wherein:
the MS is configured to:
receive an access CMD from an external source or from an internal source to access the MM; and
schedule the access CMD to the MM.
17. The IC of claim 1 further comprising:
a plurality of PEs coupled to the MM, wherein:
each of the plurality of PEs is configured to perform one or more auxiliary functions; and
at least two of the plurality of PEs are coupled in parallel to the MM.
each of the plurality of PEs is configured to execute a CMD independently from a balance of the plurality of PEs in the IC.
18. The IC of claim 17 further comprising:
a local data memory (LDM) coupled to the plurality PEs; and wherein:
data stored in the LDM is not stored in the MM and is not cached data from an off-chip memory.
19. The IC of claim 17 further comprising:
a plurality of PE clusters (PECs); and
a plurality of LDMs; and wherein:
each of the plurality of PECS comprises four PEs coupled to each other and at least a single LDM coupled to the four PEs;
the plurality of PECs is eight PECS; and
any of the PEs in any of the PECS can access data stored in any of the plurality of LDMs.
20. An integrated circuit (IC) comprising:
an input interface for receiving an external command and optional external data;
a main memory (MM) coupled to the input interface, the MM comprising:
a plurality of memory cells configured to store data; and
a memory controller (MC) configured to execute an access command to one or more of the plurality of memory cells;
a coprocessor (CP) coupled to the input interface and the MM, the coprocessor comprising:
a processing engine (PE) coupled to the MM, wherein the processing engine is configured to execute a command for a subroutine call on data without requiring an interrupt;
an output interface for transmitting data, the output interface coupled to the MM and the PE; and wherein:
the input interface comprises an input buffer memory;
the input buffer memory is partitioned into a plurality of coarse grain multi-threaded scheduling domains;
the output interface includes an output buffer memory;
the output buffer memory is partitioned into a plurality of coarse grain multi-threaded scheduling domains;
the scheduling domains of the input interface are paired with the scheduling domains of the output interface;
a scheduling domain ID is tagged to:
data stored in a given scheduling domain of the input buffer memory;
data accessed from the MM that is associated with a command (CMD) from one of the scheduling domains of the input buffer memory;
data processed by the PE that is associated with a CMD from one of the scheduling domains of the input buffer memory; and
data forwarded to the output buffer memory that is associated with a CMD from one of the scheduling domains of the input buffer memory.