Method and controller for recovering data in event of program failure and storage system using the same
A method and a controller for recovering data in event of a program failure and a storage system using the method and the controller are disclosed. The controller includes main units of a parity generator, a volatile memory module and a processor. With a parity in the volatile memory module and successfully programmed sub-data, a program failed write data can be recovered and correctly programmed. The method of the present invention has advantages of saving use of storage resources and extending lifetime of the storage system than other methods for recovering data in event of a program failure.
1. A method for recovering data in event of a program failure, comprising the steps of:
A. receiving a write data to be programmed into a plurality of non-volatile memory units;
B. generating a parity from the write data and separating the write data into a plurality of sub-data;
C. storing the parity in a volatile memory;
D. programming each of the plurality of sub-data into some of the plurality of non-volatile memory units;
E. determining if step D is successful; and
F. if the result of step E is no, recovering the sub-data in at least one program-failed non-volatile memory unit with the parity in the volatile memory and other sub-data successfully programmed, wherein the recovered sub-data is stored in a non-volatile memory unit that is not among the ones which the sub-data are programmed into.
2. The method according to claim 1 , wherein the sub-data are separated according to the specification of RAID (Redundant Array of Independent Disks) 5, RAID 6 or higher RAID level having parity information.
3. The method according to claim 1 , wherein the non-volatile memory unit is a page, a block or a plane in a flash memory chip of a SSD (Solid State Disk) or a portable storage device.
4. The method according to claim 3 , wherein the flash memory chip is a NAND flash memory chip, a NOR flash memory chip, or a charge trap flash memory chip.
5. The method according to claim 1 , wherein the volatile memory is a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory).
6. A controller for recovering data in event of a program failure, comprising:
a parity generator, for generating a parity from a write data;
a volatile memory module, for storing and providing the parity; and
a processor, electrically connected with the parity generator and the volatile memory module, for receiving a write data to be programmed into a plurality of non-volatile memory units, storing the parity in the volatile memory module, separating the write data into a plurality of sub-data, programming each of the plurality of sub-data into some of the plurality of non-volatile memory units, determining if programming each sub-data is successful, and recovering the sub-data in at least one program-failed non-volatile memory unit with the parity in the volatile memory module and other sub-data successfully programmed, wherein the recovered sub-data is stored in a non-volatile memory unit that is not among the ones which the sub-data are programmed into.
7. The controller according to claim 6 , wherein the sub-data are separated according to the specification of RAID 5, RAID 6 or higher RAID level having parity information.
8. The controller according to claim 6 , wherein the non-volatile memory unit is a page, a block or a plane in a flash memory chip of a SSD (Solid State Disk) or a portable storage device.
9. The controller according to claim 8 , wherein the flash memory chip is a NAND flash memory chip, a NOR flash memory chip, or a charge trap flash memory chip.
10. The controller according to claim 6 , wherein the volatile memory module is a DRAM module or a SRAM module.
11. The controller according to claim 6 , further comprising:
a host interface, electrically connected with the processor, for externally communicating with a host and transmitting the write data from the host to the processor; and
a non-volatile memory interface, externally connected with the plurality of non-volatile memory units and electrically connected with the processor, for bridging communication for the plurality of non-volatile memory units and the processor.
12. A storage system including the controller according to claim 11 , comprising:
the plurality of non-volatile memory units which are externally connected to the processor of the controller via the non-volatile memory interface.
13. The storage system according to claim 12 , wherein the sub-data are separated according to the specification of RAID 5, RAID 6 or higher RAID level having parity information.
14. The storage system according to claim 12 , wherein the non-volatile memory unit is a page, a block or a plane in a flash memory chip of a SSD (Solid State Disk) or a portable storage device.
15. The storage system according to claim 14 , wherein the flash memory chip is a NAND flash memory chip, a NOR flash memory chip, or a charge trap flash memory chip.
16. The storage system according to claim 12 , wherein the volatile memory module is a DRAM module or a SRAM module.