IP Library › Granted Patent US 10,114,755
Granted Patent B2
US 10,114,755 · App. 13/918,786 · Granted Oct 30, 2018

System, method, and computer program product for warming a cache for a task launch

Inventors: Scott Ricketts (San Francisco, CA); Nicholas Wang (Saratoga, CA); Shirish Gadre (Fremont, CA); Gentaro Hirota (San Francisco, CA); Robert Ohannessian, Jr. (Austin, TX)
Assignee: NVIDIA CORPORATION
G06F12/0897
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Quick Facts
Patent No.
US 10,114,755
App. No.
13/918,786
Granted
Oct 30, 2018
Kind
B2
Abstract

A system, method, and computer program product for warming a cache for a task launch is described. The method includes the steps of receiving a task data structure that defines a processing task, extracting information stored in a cache warming field of the task data structure, and, prior to executing the processing task, generating a cache warming instruction that is configured to load one or more entries of a cache storage with data fetched from a memory.

Claims (41)

1. A method comprising:

receiving, by a task management unit within a parallel processor, a task data structure that defines a processing task;

extracting information stored in a cache warming field of the task data structure; and

generating, by the task management unit prior to execution of the processing task by a processing core within the parallel processor, a cache warming instruction that is configured to load one or more entries of a cache storage with data fetched from a memory when executed by the processing core.

2. The method of claim 1 , further comprising, prior to generating the cache warming instruction, activating the processing task so that the processing task is eligible to be launched.

3. The method of claim 1 , wherein the cache storage is configured to store constants referenced by the processing task.

4. The method of claim 1 , wherein the cache storage is configured to store program instructions for the processing task.

5. The method of claim 1 , wherein the information includes a number of cache entries to load and the number of cache entries to load is an operand of the cache warming instruction.

6. The method of claim 1 , wherein the information includes an offset address within a portion of the memory that stores program instructions for the processing task and the offset address is an operand of the cache warming instruction.

7. The method of claim 1 , wherein the information includes an offset address within a portion of the memory that stores constants referenced by the processing task and the offset address is an operand of the cache warming instruction.

8. The method of claim 1 , wherein the information indicates that cache warming is enabled for the processing task.

9. The method of claim 1 , further comprising:

receiving, by the processing core, the cache warming instruction;

determining that the cache warming instruction should be ignored; and

discarding the cache warming instruction.

10. The method of claim 1 , further comprising:

receiving, by the processing core, the cache warming instruction;

determining that the cache warming instruction should be executed;

fetching the data from the memory according to the cache warming instruction; and

storing the data in one or more entries of the cache storage.

11. The method of claim 1 , further comprising launching the processing task for execution by the processing core, wherein the launching occurs at least 50 clock cycles after the cache warming instruction is generated.

12. A system, comprising:

a memory;

a parallel processor comprising:

processing cores;

a cache storage coupled to the memory; and

a task management unit configured to:

receive a task data structure that defines a processing task;

extract information stored in a cache warming field of the task data structure; and

generate, prior to execution of the processing task by at least one of the processing cores, a cache warming instruction that is configured to load one or more entries of the cache storage with data fetched from the memory when executed by at least one of the processing cores.

13. The system of claim 12 , wherein, before generating the cache warming instruction, the task management unit is further configured to activate the processing task so that the processing task is eligible to be launched.

14. The system of claim 12 , wherein the cache storage is configured to store constants referenced by the processing task.

15. The system of claim 12 , wherein the cache storage is configured to store program instructions for the processing task.

16. The system of claim 12 , wherein the information includes a number of cache entries to load and the number of cache entries to load is an operand of the cache warming instruction.

17. The system of claim 12 , wherein the information includes an offset address within a portion of the memory that stores program instructions for the processing task and the offset address is an operand of the cache warming instruction.

18. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform steps comprising:

receiving, by a task management unit within a parallel processor, a task data structure that defines a processing task;

extracting information stored in a cache warming field of the task data structure; and

generating, by the task management unit prior to execution of the processing task by a processing core within the parallel processor, a cache warming instruction that is configured to load one or more entries of a cache storage with data fetched from a memory when executed by the processing core.

19. The method of claim 1 , further comprising broadcasting the cache warming instruction to multiple processing cores.

20. The system of claim 12 , further comprising a work distribution unit that is coupled between the task management unit and the processing cores and configured to broadcast the cache warming instruction to at least two of the processing cores.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2013
From: RICKETTS, SCOTT; WANG, NICHOLAS; GADRE, SHIRISH; HIROTA, GENTARO; OHANNESSIAN, ROBERT, JR.
To: NVIDIA CORPORATION
Reel/Frame 031022/0028 →
Continuity (1)
Related Publication 20140372703A1 · Dec 18, 2014