Liquid crystal display device for improving the characteristics of gate drive voltage

1. A liquid crystal display device comprising:

a liquid crystal display panel in which a plurality of gate lines are formed;

a controller configured to generate at least four clock signals with difference phases, wherein at least one clock signal among the at least four clock signals overlaps with another one of the at least four clock signals by at least one period of a horizontal synchronous cycle;

a first gate driver configured to apply a high gate voltage to (2k−1)th gate line in response to at least two of the clock signals from the controller, the ‘k’ being a natural number greater than zero;

a second gate driver configured to apply the high gate voltage to (2k)th gate line in response to the others of the clock signals from the controller, wherein the first gate driver and the second gate driver are disposed at opposite edges of the liquid crystal display panel;

left discharge circuits each configured to apply a low gate voltage to the (2k)th gate line in response to a carry signal opposite to a voltage level on (2k+2)th gate line; and

right discharge circuits each configured to apply the low gate voltage to the (2k−1)th gate line in response to the carry signal opposite to the voltage level on (2k+1)th gate line,

wherein the first gate driver includes a plurality of left stages having a left stage including a gate output portion to output the high gate voltage to the (2k+1)th gate line and a carry output portion to output the carry signal to a right discharge circuit connected to the (2k−1)th gate line,

wherein the second gate driver includes a plurality of right stages having a right stage including a gate output portion to output the high gate voltage to the (2k+2)th gate line and a carry output portion to output the carry signal to a left discharge circuit connected to the (2k)th gate line,

wherein the gate output portion and the carry output portion of each of the plurality of left and right stages are separated from each other, and the carry output portion of each of the plurality of left and right stages is not connected to any of the plurality of gate lines, and

wherein opposite ends of each gate line among the plurality of gate lines are configured to simultaneously receive a low voltage from a corresponding stage among the plurality of left stages and the plurality of right stages and a low voltage from a corresponding discharge circuit among left and right discharge circuits.

2. The liquid crystal display device of claim 1 , wherein the at least fourth clock signals include first through fourth clock signals which have, high intervals which each correspond to two horizontal synchronous cycles and overlap with one another by a period of a single horizontal synchronous cycle.

3. The liquid crystal display device of claim 2 , wherein the first gate driver receives the first and third clock signals from the controller, and the second gate driver receives the second and fourth clock signals from the controller.

4. The liquid crystal display device of claim 1 , wherein the first gate driver further includes a left dummy stage connected to at least one of the right discharge circuits, and the second gate driver further includes a right dummy stage connected to at least one of the left discharge circuits.

5. The liquid crystal display device of claim 1 , wherein the left discharge circuits each include a transistor which includes:

a first electrode connected to the (2k)th gate line;

a second electrode configured to receive the low gate voltage; and

a gate electrode connected to the carry output portion opposite to the (2k+2)th gate line.

6. The liquid crystal display device of claim 1 , wherein the right discharge circuits each include a transistor which includes:

a first electrode connected to the (2k−1)th gate line;

a second electrode configured to receive the low gate voltage; and

a gate electrode connected to the carry output portion opposite to the (2k+1)th gate line.