IP Library › Granted Patent US 10,115,830
Granted Patent B2
US 10,115,830 · App. 14/808,246 · Granted Oct 30, 2018

Semiconductor device, manufacturing method thereof, and electronic device

Inventor: Shunpei Yamazaki (Tokyo, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/7869H01L27/127H01L29/66969H01L27/1225H01L29/24
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Quick Facts
Patent No.
US 10,115,830
App. No.
14/808,246
Granted
Oct 30, 2018
Kind
B2
Abstract

A gate insulating film is formed over an oxide semiconductor film. A gate electrode is formed over the gate insulating film. An interlayer insulating film is formed over the oxide semiconductor film and the gate electrode. Planarization treatment is performed on the interlayer insulating film. An opening is formed in the interlayer insulating film subjected to the planarization treatment. A conductive film is formed in the opening and over the interlayer insulating film subjected to the planarization treatment. A pair of conductive films is formed by performing planarization treatment on the conductive film. A first region and a second region are formed in the oxide semiconductor film by adding an impurity to the pair of conductive films. The second region and the opening overlap with each other. The second region is formed by an impact caused by addition of the impurity to the pair of conductive films.

Claims (54)

1. A method for manufacturing a semiconductor device, comprising:

forming an oxide semiconductor film;

forming a gate insulating film over the oxide semiconductor film;

forming a gate electrode over the gate insulating film;

forming an interlayer insulating film over the oxide semiconductor film and the gate electrode;

performing planarization treatment on the interlayer insulating film;

forming a first opening and a second opening in the interlayer insulating film subjected to the planarization treatment;

forming a first conductive film in the first opening and the second opening and over the interlayer insulating film subjected to the planarization treatment;

forming a second conductive film and a third conductive film by performing planarization treatment on the first conductive film; and

forming a first region and a second region in the oxide semiconductor film by adding an impurity to the second conductive film and the third conductive film,

wherein the first region and the first opening overlap with each other, and

wherein the first region is formed by an impact caused by addition of the impurity to the second conductive film.

2. The method for manufacturing a semiconductor device, according to claim 1 , wherein the impurity is added by an ion doping method or an ion implantation method.

3. The method for manufacturing a semiconductor device, according to claim 1 , wherein the impurity is argon.

4. The method for manufacturing a semiconductor device, according to claim 1 ,

wherein resistance of the first region of the oxide semiconductor film is lower than resistance of a third region of the oxide semiconductor film, and

wherein the gate electrode and the third region of the oxide semiconductor film overlap with each other.

5. A method for manufacturing a semiconductor device, comprising:

forming a gate electrode;

forming a gate insulating film over the gate electrode;

forming an oxide semiconductor film over the gate insulating film;

forming an interlayer insulating film over the oxide semiconductor film;

performing planarization treatment on the interlayer insulating film;

forming a first opening and a second opening in the interlayer insulating film subjected to the planarization treatment;

forming a first conductive film in the first opening and the second opening and over the interlayer insulating film subjected to the planarization treatment;

forming a second conductive film and a third conductive film by performing planarization treatment on the first conductive film; and

forming a first region and a second region in the oxide semiconductor film by adding an impurity to the second conductive film and the third conductive film,

wherein the first region and the first opening overlap with each other, and

wherein the first region is formed by an impact caused by addition of the impurity to the second conductive film.

6. The method for manufacturing a semiconductor device, according to claim 5 , wherein the impurity is added by an ion doping method or an ion implantation method.

7. The method for manufacturing a semiconductor device, according to claim 5 , wherein the impurity is argon.

8. The method for manufacturing a semiconductor device, according to claim 5 ,

wherein resistance of the first region of the oxide semiconductor film is lower than resistance of a third region of the oxide semiconductor film, and

wherein the gate electrode and the third region of the oxide semiconductor film overlap with each other.

9. A method for manufacturing a semiconductor device, comprising:

forming an oxide semiconductor film;

forming an interlayer insulating film over the oxide semiconductor film;

forming a first opening and a second opening in the interlayer insulating film;

forming a first conductive film in the first opening and the second opening and over the interlayer insulating film;

forming a second conductive film in the first opening and a third conductive film in the second opening by removing part of the first conductive film and dividing the first conductive film; and

adding an impurity to the second conductive film and the third conductive film to form a first region and a second region in the oxide semiconductor film,

wherein the impurity is argon,

wherein the first region of the oxide semiconductor film is in contact with the second conductive film,

wherein the second region of the oxide semiconductor film is in contact with the third conductive film,

wherein a third region of the oxide semiconductor film is between the first region and the second region of the oxide semiconductor film,

wherein resistance of the first region of the oxide semiconductor film is lower than resistance of the third region of the oxide semiconductor film,

wherein resistance of the second region of the oxide semiconductor film is lower than the resistance of the third region of the oxide semiconductor film, and

wherein the second conductive film and the third conductive film are formed by performing planarization treatment on the first conductive film.

10. The method for manufacturing a semiconductor device, according to claim 9 , wherein the impurity is added by an ion doping method or an ion implantation method.

11. The method for manufacturing a semiconductor device, according to claim 9 , further comprising forming a gate electrode before forming the oxide semiconductor film.

12. The method for manufacturing a semiconductor device, according to claim 9 , further comprising forming a gate electrode after forming the oxide semiconductor film.

13. The method for manufacturing a semiconductor device, according to claim 9 ,

wherein the first region is formed in the oxide semiconductor film by an impact caused by addition of the impurity to the second conductive film, and

wherein the second region is formed in the oxide semiconductor film by an impact caused by addition of the impurity to the third conductive film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2015
From: YAMAZAKI, SHUNPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 036221/0947 →
Priority Claims (1)
JP 2014-153753 · Jul 29, 2014 · national
Continuity (1)
Related Publication 20160035896A1 · Feb 4, 2016
Cited By (1)
US 12,433,019