Memory devices, systems and methods employing command/address calibration
During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.
1. An interface training method for a semiconductor memory device, comprising:
receiving a clock signal by the semiconductor memory device;
receiving a first calibration signal along with the clock signal through command/address terminals of the semiconductor memory device, and detecting and latching a logic level of the first calibration signal at a rising edge of the clock signal;
sending a second calibration signal to an external device through data terminals of the semiconductor memory device, the second calibration signal being based on the latched logic level of the first calibration signal; and
receiving command/address signals through the command/address terminals of the semiconductor memory device along with the clock signal, a phase between the command/address signals and the clock signal having been modified in response to the second calibration signal,
wherein the semiconductor memory device further receives a read request signal over a first terminal separate from the command/address terminals of the semiconductor memory device while receiving the first calibration signal.
2. The interface training method of claim 1 , wherein the first terminal is configured to receive a clock enable signal from the external device.
3. The interface training method of claim 2 , wherein the clock enable signal is activated during receiving the first calibration signal.
4. The interface training method of claim 3 , wherein the command/address terminals includes CA 0 , CA 1 , CA 2 , CA 3 , CA 4 and CA 5 .
5. The interface training method of claim 4 , wherein the data terminals includes DQ 8 , DQ 9 , DQ 10 , DQ 11 , DQ 12 and DQ 13 .
6. The interface training method of claim 1 , further detecting and latching the logic level of the first calibration signal at a falling edge of the clock signal.
7. The interface training method of claim 6 , wherein the first calibration signal comprises a sequence of data packets transmitted in a double data rate speed.
8. The interface training method of claim 7 , wherein the command/address terminals includes CA 0 , CA 1 , CA 2 , CA 3 , CA 4 , CA 5 , CA 6 , CA 7 , CA 8 and CA 9 .
9. The interface training method of claim 8 , wherein the second calibration signal is sent through a first set of data terminals at rising edge of the clock signal and sent through a second set of data terminals at falling edge of the clock signal, the first set of data terminals includes DQ 0 , DQ 2 , DQ 4 , DQ 6 , DQ 8 , DQ 10 , DQ 12 and DQ 14 , and the second set of data terminals includes DQ 1 , DQ 3 , DQS, DQ 7 , DQ 9 , DQ 11 , DQ 13 and DQ 15 .
10. An interface training method for a semiconductor memory device, comprising:
receiving a clock signal by the semiconductor memory device;
receiving a first calibration signal along with the clock signal through command/address terminals of the semiconductor memory device, and detecting and latching a logic level of the first calibration signal at a rising edge of the clock signal;
sending a second calibration signal to an external device through data terminals of the semiconductor memory device, the second calibration signal being based on the latched logic level of the first calibration signal; and
receiving command/address signals through the command/address terminals of the semiconductor memory device along with the clock signal, a phase between the command/address signals and the clock signal having been modified in response to the second calibration signal,
wherein the receiving of the first calibration signal includes receiving a training pattern through the command/address terminals, and the training pattern includes at least two signals having different logic levels from each other.
11. The interface training method of claim 10 , wherein the receiving of the command/address signals through the command/address terminals comprises individually adjusting the phase between each of the command/address signals and the clock signal.
12. The interface training method of claim 11 , wherein the receiving of the command/address signals through the command/address terminals comprises receiving a first signal over a first line connected to first command/address terminal with a first phase with respect to the clock signal and receiving a second signal over a second line connected to second command/address terminal with a second phase with respect to the clock signal.
13. The interface training method of claim 12 , wherein the command/address terminals includes CA 0 , CA 1 , CA 2 , CA 3 , CA 4 and CA 5 .
14. The interface training method of claim 13 , wherein the data terminals includes DQ 8 , DQ 9 , DQ 10 , DQ 11 , DQ 12 and DQ 13 .
15. The interface training method of claim 10 , further detecting and latching the logic level of the first calibration signal at a falling edge of the clock signal.
16. The interface training method of claim 15 , wherein the first calibration signal comprises a sequence of data packets transmitted in a double data rate speed.
17. The interface training method of claim 16 , wherein the command/address terminals includes CA 0 , CA 1 , CA 2 , CA 3 , CA 4 , CA 5 , CA 6 , CA 7 , CA 8 and CA 9 .
18. The interface training method of claim 17 , wherein the second calibration signal is sent through a first set of data terminals at rising edge of the clock signal and sent through a second set of data terminals at falling edge of the clock signal, the first set of data terminals includes DQ 0 , DQ 2 , DQ 4 , DQ 6 , DQ 8 , DQ 10 , DQ 12 and DQ 14 , and the second set of data terminals includes DQ 1 , DQ 3 , DQS, DQ 7 , DQ 9 , DQ 11 , DQ 13 and DQ 15 .
19. An interface training method for a semiconductor memory device, comprising:
receiving a clock signal by the semiconductor memory device;
receiving a first calibration signal along with the clock signal through command/address terminals of the semiconductor memory device, and detecting and latching a logic level of the first calibration signal at a rising edge of the clock signal;
sending a second calibration signal to an external device through data terminals of the semiconductor memory device, the second calibration signal being based on the latched logic level of the first calibration signal; and
receiving command/address signals through the command/address terminals of the semiconductor memory device along with the clock signal, a phase between the command/address signals and the clock signal having been modified in response to the second calibration signal,
wherein receiving the first calibration signal includes receiving both a portion of address information and a portion of command information through one command/address terminal.
20. The interface training method of claim 19 , wherein further detecting and latching the logic level of the first calibration signal at a falling edge of the clock signal, and the first calibration signal comprises a sequence of data packets transmitted in a double data rate speed.