Semiconductor device and IO-cell
According to an aspect, a semiconductor device and an IO-cell include a plurality of first power supply lines and a plurality of second power supply lines alternately arranged in a first direction, the first and second power supply lines each being supplied with electric power in which the voltage of the electric power supplied to the first power supply is different from that supplied to the second power supply, and a third power supply line formed in a wiring layer different from a wiring layer in which the first and second power supply lines are arranged, the third power supply line being connected to adjacent first power supply lines among the plurality of first power supply lines through a via, in which all of the first, second and third power supply lines are formed so as to extend in a second direction perpendicular to the first direction.
1. A semiconductor device comprising:
a first wiring layer in which a plurality of first power supply lines connected to a first electric power and a plurality of second power supply lines connected to a second electric power are arranged side-by-side in a first direction with first power supply lines being alternated with second power supply lines in said first direction;
a second wiring layer in which a third power supply line is disposed, the third power supply line being electrically connected through vias to spaced apart first and second ones of said plurality of first power supply lines, and
an upper wiring layer formed over the second wiring layer, the upper wiring layer having an upper layer power supply line connected to the first electric power, the upper layer power supply line being electrically connected through vias to the third power supply line of the second wiring layer, wherein
the first electric power is different from the second electric power;
in the first wiring layer, a single second power supply line, and no other intervening conductive line, is disposed between said spaced apart first and second ones of said plurality of first power supply lines to which the third power supply line is electrically connected through vias,
each of the first, second and third power supply lines is formed such that a longest dimension is in a second direction perpendicular to the first direction, each power supply line having cross-wise sides extending along the longest dimension,
in a top view, the plurality of first power supply lines have a concavo-convex shape along their cross-wise sides,
the upper layer power supply line does not have a concavo-convex shape along its sides, and
the number of vias that electrically connect the third power supply line and the upper layer power supply line is larger than the number of vias that electrically connect the first power supply line and the third power supply line.
2. The semiconductor device according to claim 1 , wherein
the third power supply line is electrically connected to convex parts of the adjacent first power supply lines through vias.
3. The semiconductor device according to claim 2 , wherein
the plurality of second power supply lines have a concavo-convex shape along at least one of their sides, and
the first and second power supply lines are arranged so that a convex part of the first power supply line engages with a concave part of the second power supply line.
4. The semiconductor device according to claim 1 , wherein
a fourth power supply line is disposed in the second wiring layer, the fourth power supply line being electrically connected through vias to spaced apart first and second ones of said plurality of second power supply lines,
in the first wiring layer, a single first power supply line, and no other intervening conductive line, is disposed between said spaced apart first and second ones of said plurality of second power supply lines to which the fourth power supply line is electrically connected through vias, and
the plurality of second power supply lines have a concavo-convex shape along at least one of their sides, and
the fourth power supply line is electrically connected to convex parts of the adjacent second power supply lines through vias.
5. The semiconductor device according to claim 1 , wherein
the third power supply line has a concavo-convex shape along at least one of its sides, and
the adjacent first power supply lines are both electrically connected to convex parts of the third power supply line through vias.
6. The semiconductor device according to claim 5 , wherein
a fourth power supply line electrically connected to adjacent second power supply lines through vias is disposed in the second wiring layer,
the fourth power supply line has a concavo-convex shape along at least one of its sides, and
the third and fourth power supply lines are arranged so that a convex part of the third power supply line engages with a concave part of the fourth power supply line.
7. The semiconductor device according to claim 1 , wherein
the first direction is a direction perpendicular to a side of a semiconductor chip,
the second direction is a direction parallel to the side of the semiconductor chip, and
all of the first, second and third power supply lines are formed so as to extend along a periphery of a semiconductor chip.
8. The semiconductor device according to claim 1 , wherein
the first wiring layer is formed in a layer below the second wiring layer, and
the third power supply line is formed above the second power supply line.
9. The semiconductor device according to claim 1 , wherein the second wiring layer includes a plurality of wiring layers.
10. The semiconductor device according to claim 1 , wherein
at least one of the first to third power supply lines includes a convex part along its side,
the convex part includes a wide part at its tip, the wide part having a larger line width than that of a base part of the convex part, and
a via for electrically connecting to a line provided in another wiring layer is formed in the wide part.
11. An IO-cell comprising at least a buffer circuit formed therein, the IO-cell further comprising:
a first wiring layer in which a plurality of first power supply lines for supplying a first electric power to the buffer circuit and a plurality of second power supply lines for supplying a second electric power to the buffer circuit are arranged side-by-side in a first direction with the first power supply lines being alternated with the second power supply lines in said first direction;
a second wiring layer in which a third power supply line is disposed, the third power supply line being electrically connected through vias to spaced apart first and second ones of said plurality of first power supply lines, and
an upper wiring layer formed over the second wiring layer, the upper wiring layer having an upper layer power supply line connected to the first electric power, the upper layer power supply line being electrically connected through vias to the third power supply line of the second wiring layer, wherein
the first electric power is different from the second electric power; in the first wiring layer, a single second power supply line, and no other intervening conductive line, is disposed between said spaced apart first and second ones of said plurality of first power supply lines to which the third power supply line is electrically connected through vias,
each of the first, second and third power supply lines is formed such that a longest dimension is in a second direction perpendicular to the first direction, each power supply line having cross-wise sides extending along the longest dimension,
in a top view, the plurality of first power supply lines have a concavo-convex shape along their cross-wise sides,
the upper layer power supply line does not have a concavo-convex shape along its sides, and the number of vias that electrically connect the third power supply line and the upper layer power supply line is larger than the number of vias that electrically connect the first power supply line and the third power supply line.
12. The IO-cell according to claim 11 , wherein
the third power supply line is electrically connected to convex parts of the adjacent first power supply lines through vias.
13. The IO-cell according to claim 12 , wherein
the plurality of second power supply lines have a concavo-convex shape along at least one of their sides, and
the first and second power supply lines are arranged so that a convex part of the first power supply line engages with a concave part of the second power supply line.
14. The IO-cell according to claim 11 , wherein
a fourth power supply line is disposed in the second wiring layer, the fourth power supply line being electrically connected through vias to spaced apart first and second ones of said plurality of second power supply lines,
in the first wiring layer, a single first power supply line, and no other intervening conductive line, is disposed between said spaced apart first and second ones of said plurality of second power supply lines to which the fourth power supply line is electrically connected through vias,
the plurality of second power supply lines have a concavo-convex shape along at least one of their sides, and
the fourth power supply line is electrically connected to convex parts of the adjacent second power supply lines through vias.
15. The IO-cell according to claim 11 , wherein
the third power supply line has a concavo-convex shape along at least one of its sides, and
the adjacent first power supply lines are both electrically connected to convex parts of the third power supply line through vias.
16. The IO-cell according to claim 15 , wherein
a fourth power supply line electrically connected to adjacent second power supply lines through vias is disposed in the second wiring layer,
the fourth power supply line has a concavo-convex shape along at least one of its sides, and
the third and fourth power supply lines are arranged so that a convex part of the third power supply line engages with a concave part of the fourth power supply line.
17. The IO-cell according to claim 11 , wherein the first, second and third power supply lines are connected to the first, second and third power supply lines, respectively, of another IO-cell disposed adjacent to the IO-cell.
18. The IO-cell according to claim 11 , wherein
the first wiring layer is formed in a layer below the second wiring layer, and
the third power supply line is formed above the second power supply line.
19. The IO-cell according to claim 11 , wherein
the second wiring layer includes a plurality of wiring layers.
20. The IO-cell according to claim 11 , wherein
at least one of the first to third power supply lines includes a convex part along its side,
the convex part includes a wide part at its tip, the wide part having a larger line width than that of a base part of the convex part, and
a via for electrically connecting to a line provided in another wiring layer is formed in the wide part.
21. The IO-cell according to claim 11 , wherein:
at least one of the first to third power supply lines has a concavo-convex shape along at least one of its sides.
22. The semiconductor device according to claim 1 , wherein:
at least one of the first to third power supply lines has a concavo-convex shape along at least one of its sides.
23. The semiconductor device according to claim 1 , wherein
a first of the first power supply lines has a concavo-convex shape along both of its sides;
a first of the second power supply lines has a concavo-convex shape along both of its sides; and
concavo-convex parts on one side of said first of the first power supply lines engage concavo-convex parts on a facing side of said first of the second power supply lines.
24. The IO-cell according to claim 11 , wherein:
a first of the first power supply lines has a concavo-convex shape along both of its sides;
a first of the second power supply lines has a concavo-convex shape along both of its sides; and
concavo-convex parts on one side of said first of the first power supply lines engage concavo-convex parts on a facing side of said first of the second power supply lines.