IP Library › Granted Patent US 10,121,905
Granted Patent B2
US 10,121,905 · App. 14/474,800 · Granted Nov 6, 2018

Semiconductor device

Inventor: Hiroyuki Miyake (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/788H01L29/78648G09G3/3233G09G2300/0861G09G2300/0866H01L27/1255H01L29/7869
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Quick Facts
Patent No.
US 10,121,905
App. No.
14/474,800
Granted
Nov 6, 2018
Kind
B2
Abstract

Provided is a semiconductor device including a transistor in which a first gate and a second gate are provided with a channel formation region provided therebetween and which achieves both control of the threshold voltage and an increase in the on-state current. In a period during which first voltage with which the transistor is turned off is supplied to the first gate, control voltage for controlling the threshold voltage is supplied to the second gate. In a period during which second voltage with which the transistor is turned on is supplied to the first gate, the second voltage is supplied to the first gate and voltage in which voltage based on change in the voltage of a signal supplied to the first gate is added to the control voltage is supplied to the second gate.

Claims (33)

1. A semiconductor device comprising:

a first transistor comprising a first gate and a second gate; and

a source follower circuit electrically connected to the first transistor, the source follower circuit comprising a second transistor and a third transistor,

wherein the second transistor and the third transistor are connected in series,

wherein the first gate is electrically connected to the second gate through the source follower circuit,

wherein a channel formation region of the first transistor is provided between the first gate and the second gate,

wherein in a first period during which a first voltage with which the first transistor is turned off is supplied to the first gate, a control voltage is supplied to the second gate,

wherein in a second period during which a second voltage with which the first transistor is turned on is supplied to the first gate, a third voltage is supplied to the second gate, and

wherein the second voltage is different from the third voltage.

2. The semiconductor device according to claim 1 ,

wherein an input terminal of the source follower circuit is electrically connected to the first gate, and

wherein an output terminal of the source follower circuit is electrically connected to the second gate.

3. The semiconductor device according to claim 1 , wherein the first transistor comprises an oxide semiconductor in the channel formation region.

4. The semiconductor device according to claim 1 , wherein the third voltage is higher than the control voltage.

5. The semiconductor device according to claim 1 , wherein the third voltage changes in accordance with a change of a voltage of the first gate.

6. The semiconductor device according to claim 1 , wherein the second gate is electrically floating in the second period.

7. A semiconductor device comprising:

a first transistor comprising a first gate and a second gate; and

a source follower circuit electrically connected to the first transistor, the source follower circuit comprising a second transistor and a third transistor,

wherein the second transistor and the third transistor are connected in series,

wherein the first gate is electrically connected to the second gate through the source follower circuit,

wherein the second gate is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the third transistor,

wherein a channel formation region of the first transistor is provided between the first gate and the second gate,

wherein in a first period during which a first voltage with which the first transistor is turned off is supplied to the first gate, a control voltage is supplied to the second gate,

wherein in a second period during which a second voltage with which the first transistor is turned on is supplied to the first gate, a third voltage is supplied to the second gate, and

wherein the second voltage is different from the third voltage.

8. The semiconductor device according to claim 7 ,

wherein an input terminal of the source follower circuit is electrically connected to the first gate, and

wherein an output terminal of the source follower circuit is electrically connected to the second gate.

9. The semiconductor device according to claim 7 , wherein the first transistor comprises an oxide semiconductor in the channel formation region.

10. The semiconductor device according to claim 7 , wherein the third voltage is higher than the control voltage.

11. The semiconductor device according to claim 7 , wherein the third voltage changes in accordance with a change of a voltage of the first gate.

12. The semiconductor device according to claim 7 , wherein the second gate is electrically floating in the second period.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 2, 2014
From: MIYAKE, HIROYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 033651/0372 →
Priority Claims (1)
JP 2013-183030 · Sep 20, 2013 · national
Continuity (1)
Related Publication 20150060847A1 · Mar 5, 2015