Semiconductor device
A semiconductor device includes a substrate including a cell region and a peripheral region adjacent to the cell region, a cell stack structure located in the cell region, the cell stack structure including vertical memory strings, a circuit located in the peripheral region, the circuit driving the vertical memory strings, and an interlayer insulating layer formed on the substrate to cover the cell stack structure and the circuit, and including air gaps located between the cell region and the peripheral region.
1. A semiconductor device comprising:
a substrate including a cell region and a peripheral region adjacent to the cell region;
a cell stack structure located in the cell region, and including memory strings;
a circuit located in the peripheral region; and
an interlayer insulating layer formed on the substrate to cover the cell stack structure and the circuit, and including air gaps located between the cell region and the peripheral region,
wherein the air gaps include:
first air gaps having an island shape and arranged along a first direction;
second air gaps having an island shape and arranged along the first direction, and
wherein the second air gaps are next to the first air gaps in a second direction crossing the first direction, and are arranged to be offset from the first air gaps in the first direction.
2. The semiconductor device of claim 1 ,
wherein the cell region has a quadrangular shape having first to fourth sides, and
wherein the air gaps include at least one of third to sixth air gaps, wherein the third air gap extends along the first side of the cell region in that the first direction, the fourth air gap extends along the second side of the cell region in a second direction crossing the first direction, the fifth air gap extends along the third side of the cell region in the first direction, and the sixth air gap extends along the fourth side of the cell region in the second direction.
3. The semiconductor device of claim 1 ,
wherein the cell region has a quadrangular shape having first to fourth sides, and
wherein the first air gaps are arranged along the first side of the cell region and extend in the first direction, and the second air gaps are arranged along the third side of the cell region in the first direction.
4. The semiconductor device of claim 1 ,
wherein the cell region has a quadrangular shape having first to fourth sides, and
wherein the air gaps include at least one third air gap having a closed loop shape surrounding the first to fourth sides of the cell region.
5. The semiconductor device of claim 1 ,
wherein the cell region has a quadrangular shape having first to fourth sides, and
wherein the air gaps surround the first to fourth sides of the cell region.
6. The semiconductor device of claim 1 , further comprising:
isolation layers formed in the substrate between the cell region and the peripheral region,
wherein the air gaps are located over the isolation layers to overlap with the isolation layers in the stacking direction of the cell stack structure.
7. The semiconductor device of claim 1 , wherein the air gaps extend in the stacking direction of the cell stack structure, and have a height substantially equal to or higher than that of the cell stack structure.
8. The semiconductor device of claim 1 , wherein the air gaps extend in the stacking direction of the cell stack structure, and have a height less than that of the cell stack structure.
9. The semiconductor device of claim 1 , further comprising:
a pad stack structure formed on a contact region of the substrate, wherein the contact region is located between the cell region and the peripheral region; and
contact plugs connected to the pad structure, wherein a bias is applied to the vertical memory strings through the contact plugs.
10. A semiconductor device, comprising:
a substrate including a cell region and a peripheral region adjacent to the cell region;
a cell stack structure located in the cell region, and including memory strings;
a circuit located in the peripheral region; and
an interlayer insulating layer formed on the substrate to cover the cell stack structure and the circuit, and including air gaps;
a pad stack structure formed on a contact region of the substrate, wherein the contact region is located between the cell region and the peripheral region; and
contact plugs connected to the pad structure,
wherein the air gap is located in the contact region between the contact plugs.
11. The semiconductor device of claim 1 ,
wherein the pad stack structure has the shape of steps, and
wherein each of the air gaps is located in each of the steps of the pad stack structure.
12. The semiconductor device of claim 1 , wherein the circuit is an X-decoder.
13. The semiconductor device of claim 1 , wherein the circuit is a page buffer.
14. A semiconductor device comprising:
a substrate;
a stack structure formed over the substrate;
an interlayer insulating layer formed on the substrate to cover the stack structure; and
flexible buffers located at the periphery of the stack structure, and formed in the interlayer insulating layer to buffer stress applied to the stack structure from the interlayer insulating layer,
wherein the flexible buffers have an island shape and are arranged along a sidewall of the stack structure so that the flexible buffers are spaced apart from each other.
15. The semiconductor device of claim 14 , wherein a shape of each of the flexible buffers is modified by the stress.
16. The semiconductor device of claim 14 , wherein each of the flexible buffers is an air gap.
17. The semiconductor device of claim 14 , wherein each of the flexible buffers has a height substantially equal to or higher than that of the stack structure.
18. The semiconductor device of claim 1 , wherein at least two layers of the air gaps surround the cell structure.