IP Library Granted Patent US 10,128,328
Granted Patent B2
US 10,128,328 · App. 15/793,530 · Granted Nov 13, 2018

Method of manufacturing semiconductor devices and semiconductor device containing hydrogen-related donors

Inventors: Moriz Jelinek (Villach, AT); Hans Weber (Bayerisch Gmain, DE); Hans-Joachim Schulze (Taufkirchen, DE); Johannes Georg Laven (Taufkirchen, DE); Werner Schustereder (Villach, AT)
Assignee: Infineon Technologies AG
H01L29/0615H01L21/2253H01L21/26513H01L21/3003H01L21/324H01L21/78H01L22/14H01L29/0684H01L29/0847H01L29/1095H01L29/167H01L29/32H01L29/36H01L29/66143H01L29/66333H01L29/66712H01L29/7395H01L29/7811H01L29/872
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,128,328
App. No.
15/793,530
Granted
Nov 13, 2018
Kind
B2
Abstract

Crystal lattice defects are generated in a horizontal surface portion of a semiconductor substrate and hydrogen-related donors are formed in the surface portion. Information is obtained about a cumulative dopant concentration of dopants, including the hydrogen-related donors, in the surface portion. Based on the information about the cumulative dopant concentration and a dissociation rate of the hydrogen-related donors, a main temperature profile is determined for dissociating a defined portion of the hydrogen-related donors. The semiconductor substrate is subjected to a main heat treatment applying the main temperature profile to obtain, in the surface portion, a final total dopant concentration deviating from a target dopant concentration by not more than 15%.

Claims (38)

1. A method of manufacturing a semiconductor device, the method comprising:

generating crystal lattice defects in a horizontal surface portion of a semiconductor substrate;

forming hydrogen-related donors in the surface portion;

obtaining information about a cumulative dopant concentration of dopants including the hydrogen-related donors, in the surface portion;

determining, based on the information about the cumulative dopant concentration, a main temperature profile for dissociating a defined portion of the hydrogen-related donors; and

subjecting the semiconductor substrate to a main heat treatment applying the main temperature profile to obtain, in the surface portion, a final total dopant concentration deviating from a target dopant concentration by not more than 15%.

2. The method of claim 1 , wherein the surface portion contains extrinsic dopants and the cumulative dopant concentration is the sum of an extrinsic net dopant concentration and a preparatory hydrogen-related donor concentration after the forming of the hydrogen-related donors.

3. The method of claim 1 , wherein the semiconductor substrate contains extrinsic donors and an extrinsic net dopant concentration is at least 1E13 cm −3 .

4. The method of claim 1 , wherein the semiconductor substrate contains extrinsic donors and an extrinsic net dopant concentration is at most 5E12 cm −3 .

5. The method of claim 1 , wherein the semiconductor substrate is intrinsic.

6. The method of claim 1 , wherein forming the hydrogen-related donors comprises a preparatory heat treatment for diffusing hydrogen into the surface portion.

7. The method of claim 1 , wherein generating the crystal lattice defects comprises irradiating the semiconductor substrate with protons.

8. The method of claim 7 , further comprising:

after implanting the protons, thinning the semiconductor substrate from a side opposite to the front surface so that a base portion comprising an end-of-range peak of the proton implant is removed.

9. The method of claim 7 , wherein forming the hydrogen-related donors comprises a preparatory heat treatment for diffusing the implanted protons into the surface portion.

10. The method of claim 9 , wherein a maximum temperature applied in the preparatory heat treatment is above 470° C. and at most 510° C.

11. The method of claim 1 , wherein a maximum temperature applied in the main heat treatment is above 510° C.

12. The method of claim 1 , wherein at least 50% of a total duration of the main temperature profile is an isothermal process given by a constant main process temperature and a main process time for which the constant main process temperature is applied.

13. The method of claim 1 , further comprising:

forming anode/body wells in the semiconductor substrate,

wherein the anode/body wells form first pn junctions with cathode/drain structures,

wherein the cathode/drain structures comprise drift zones in the surface portion,

wherein a dopant concentration in the drift zones is equal to the final total dopant concentration.

14. The method of claim 1 , wherein the information about the cumulative dopant concentration comprises a capacitive/voltage measurement across at least one of a pn junction and a Schottky contact formed by the surface portion.

15. The method of claim 14 , wherein a contact probe is pressed against a section of the front surface exposing the surface portion.

16. The method of claim 1 , further comprising:

forming an interlayer dielectric at a front side of the semiconductor substrate before subjecting the semiconductor substrate to the main heat treatment.

17. The method of claim 1 , further comprising:

forming a plurality of separated semiconductor dies from the semiconductor substrate after subjecting the semiconductor substrate to the main heat treatment.

18. The method of claim 1 , wherein at least 25% of donors in the semiconductor substrate are hydrogen-related donors after the main heat treatment.

19. The method of claim 1 , wherein an intrinsic oxygen concentration in the semiconductor substrate is in a range from 1E17 cm −3 to 6E17 cm −3 .

20. The method of claim 1 , wherein a substitutional carbon concentration in the semiconductor substrate is in a range from 1E14 cm −3 to 5E15 cm −3 .

21. The method of claim 1 , further comprising:

after the main heat treatment, implanting protons to form a field stop layer in the semiconductor substrate.

22. The method of claim 21 , further comprising:

subjecting the semiconductor substrate to a supplementary heat treatment which activates the protons to form the field stop layer,

wherein a maximum temperature applied in the supplementary heat treatment is below 420° C.

23. The method of claim 1 , wherein the semiconductor substrate is subjected to the main heat treatment before forming a first metallization at a front side.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2017
From: JELINEK, MORIZ; WEBER, HANS; SCHULZE, HANS-JOACHIM; LAVEN, JOHANNES GEORG; SCHUSTEREDER, WERNER
To: INFINEON TECHNOLOGIES AG
Reel/Frame 044271/0671 →
Priority Claims (1)
DE 10 2016 120 771 · Oct 31, 2016 · national
Continuity (1)
Related Publication 20180122895A1 · May 3, 2018