Field effect transistor
Provided is a field-effect transistor (FET) that achieves compatibility between a higher current density and lower contact resistance and exhibits excellent properties, and a method for producing the FET. The FET includes: a channel layer above a substrate; an InAlN layer above the channel layer; an In x Al y Ga 1-(x+y) N layer on the InAlN layer, where 0<x<1, 0<y<1, and x+y<1; and a source electrode and a drain electrode formed on the In x Al y Ga 1-(x+y) N layer.
1. A field-effect transistor comprising:
a GaN layer above a substrate;
an InAlN layer above the GaN layer;
an In x Al y Ga 1-(x+y) N layer on the InAlN layer, where 0<x<1, 0<y<1, and x+y<1; and
ohmic electrodes forming ohmic contact with the In x Al y Ga 1-(x+y) N layer, and
a gate electrode over the In x Al y Ga 1-(x+y) N layer,
wherein the GaN layer is in contact with the In x Al y Ga 1-x+y) N layer in a region below the gate electrode.
2. The field-effect transistor according to claim 1 , further comprising an AIN layer between the InAlN layer and the GaN layer.
3. The field-effect transistor according to claim 1 , wherein x of the In x Al y Ga 1-(x+y) N layer increases with an increase in distance from the InAlN layer.
4. The field-effect transistor according to claim 1 ,
wherein the InAlN layer and the In x Al y Ga 1-(x+y) N layer have an opening, and
the field-effect transistor further comprises: a first semiconductor layer on the GaN layer that is exposed through the opening, the first semiconductor layer comprising a material having an amount of polarity smaller than an amount of polarity of the In x Al y Ga 1-(x+y) N layer; and
the gate electrode is disposed above the first semiconductor layer.
5. The field-effect transistor according to claim 4 , further comprising a second semiconductor layer between the first semiconductor layer and the gate electrode, the second semiconductor layer having a p-type conductivity.
6. The field-effect transistor according to claim 5 , wherein the second semiconductor layer comprises GaN.
7. The field-effect transistor according to claim 5 , further comprising an insulating film between the second semiconductor layer and the gate electrode.
8. The field-effect transistor according to claim 4 , wherein the first semiconductor layer comprises AlGaN.
9. The field-effect transistor according to claim 4 , further comprising an insulating film between the first semiconductor layer and the gate electrode.
10. The field-effect transistor according to claim 1 ,
wherein the InAlN layer and the In x Al y Ga 1-(x+y) N layer have an opening, and
the field-effect transistor further comprises an insulating film, the gate electrode being disposed through the insulating film above the GaN layer that is exposed through the opening.
11. The field-effect transistor according to claim 1 , wherein the InAlN layer lattice-matches the GaN layer.
12. The field-effect transistor according to claim 1 , wherein the In x Al y Ga 1-(x+y) N layer satisfies y>4.6x.
13. The field-effect transistor according to claim 1 , further comprising a p-type semiconductor layer between the In x Al y Ga 1-(x+y) N layer and the gate electrode.
14. The field-effect transistor according to claim 13 , wherein the p-type semiconductor layer comprises GaN.
15. The field-effect transistor according to claim 13 , further comprising an insulating film between the p-type semiconductor layer and the gate electrode.
16. The field-effect transistor according to claim 1 , further comprising
an insulating film between the In x Al y Ga 1-(x+y) N layer and the gate electrode.
17. A field-effect transistor comprising:
a GaN layer above a substrate;
an InAlN layer above the GaN layer;
an In x Al y Ga 1-(x+y) N layer on the InAlN layer, where 0<x<1, 0<y<1, and x+y<1; and
ohmic electrodes on the In x Al y Ga 1-(x+y) N layer,
wherein the InAlN layer and the In x Al y Ga 1-(x+y) N layer have an opening, and
the field-effect transistor further comprises:
a first semiconductor layer on the GaN layer that is exposed through the opening, the first semiconductor layer comprising a material having an amount of polarity smaller than an amount of polarity of the In x Al y Ga 1-(x+y) N layer;
a gate electrode above the first semiconductor layer, and
an insulating film between the first semiconductor layer and the gate electrode, and
wherein the first semiconductor layer covers both of a bottom surface and a side surface of the opening.
18. The field-effect transistor according to claim 17 , wherein the first semiconductor layer is in direct contact with the In x Al y Ga 1-(x+y) N layer.
19. A field-effect transistor comprising:
a GaN layer above a substrate;
an InAlN layer above the GaN layer;
an In x Al y Ga 1-(x+y) N layer on the InAlN layer, where 0<x<1, 0<y<1, and x+y<1; and
ohmic electrodes on the In x Al y Ga 1-(x+y) N layer,
wherein the InAlN layer and the In x Al y Ga 1-(x+y) N layer have an opening, and
the field-effect transistor further comprises:
a first semiconductor layer on the GaN layer that is exposed through the opening, the first semiconductor layer comprising a material having an amount of polarity smaller than an amount of polarity of the In x Al y Ga 1-(x+y) N layer;
a gate electrode above the first semiconductor layer,
a second semiconductor layer between the first semiconductor layer and the gate electrode, the second semiconductor layer having a p-type conductivity, and
an insulating film between the second semiconductor layer and the gate electrode.