Apparatus and method for data level shifting with boost assisted inputs for high speed and low voltage applications
The disclosure relates to a data level shifter circuit including a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal; a first input transistor including a first control signal configured to receive the input data signal; a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a node and a lower voltage rail; and a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between an upper voltage rail and the node.
1. An apparatus comprising:
a boost circuit configured to generate a boosted input data signal based on a transition of an input data signal;
a first input transistor including a first control terminal configured to receive the input data signal;
a second input transistor including a second control terminal configured to receive the boosted input data signal, wherein the first and second input transistors are coupled in parallel between a first node and a first voltage rail; and
a latch circuit configured to generate an output data signal based on the input data signal, wherein the latch circuit is coupled between a second voltage rail and the first node;
wherein the boost circuit comprises:
a third transistor coupled between a second node and the first voltage rail, wherein the third transistor includes a third control terminal configured to receive a first control signal, and wherein the second node is coupled to the second control terminal of the second transistor;
a fourth transistor coupled between a third voltage rail and the second node, wherein the fourth transistor includes a fourth control terminal configured to receive a second control signal; and
a capacitor including a first terminal configured to receive a first voltage and a second terminal coupled to the second node;
wherein the first control signal turns on the third transistor during a first time interval to discharge the capacitor, wherein the second control signal turns off the fourth transistor during the first time interval;
wherein the second control signal turns on the fourth transistor during a second time interval to allow a second voltage at the third voltage rail to charge the capacitor, wherein the first control signal turns off the third transistor during the second time interval, and wherein the first voltage is at a low logic voltage during the second time interval; and
wherein the first voltage is raised to a high logic voltage during a third time interval to generate the boosted input data signal, wherein the first and second control signals turn off the third and fourth transistors during the third time interval, respectively.
2. The apparatus of claim 1 , wherein the boost circuit is coupled between a third voltage rail and the first voltage rail.
3. The apparatus of claim 2 , wherein a supply voltage at the second voltage rail is greater than a supply voltage at the third voltage rail.
4. The apparatus of claim 3 , wherein the boosted input signal swings between a high logic voltage and a low logic voltage, wherein the high logic voltage is greater than the supply voltage at the third voltage rail.
5. The apparatus of claim 1 , wherein the input data signal swings between a first set of high and low logic voltages in accordance with a first voltage domain, wherein the output data signal swings between a second set of high and low logic voltages, wherein the high logic voltage of the second set is greater than the high logic voltage of the first set.
6. The apparatus of claim 5 , wherein the boosted input data signal swings between a third set of high and low logic voltages, wherein the high logic voltage of the third set is greater than the high logic voltage of the first set.
7. The apparatus of claim 1 , wherein the boost circuit further comprises a fifth transistor coupled between the second node and the third transistor, wherein the fifth transistor includes a fifth control terminal configured to receive a substantially constant bias voltage.
8. The apparatus of claim 1 , further comprising a driver circuit configured to generate the second control signal and the first voltage based on the input data signal.
9. The apparatus of claim 8 , wherein the driver circuit comprises:
a first inverter including an input configured to receive the input data signal;
a first delay element including an input coupled to an output of the first inverter;
a NAND gate including a first input coupled to an output of the first delay element, a second input configured to receive the input data signal, and an output configured to generate the second control signal;
a second delay element including an input coupled to the output of the first delay element; and
a second inverter including an input coupled to an output of the second delay element and an output configured to generate the first voltage.
10. The apparatus of claim 8 , wherein the driver circuit comprises:
a first inverter including an input configured to receive the input data signal;
a first delay element including an input coupled to an output of the first inverter;
an OR gate including a first input coupled to an output of the first delay element, a second input configured to receive the input data signal, and an output configured to generate the second control signal; and
a second delay element including an input coupled to the output of the first delay element, and an output configured to generate the first voltage.
11. The apparatus of claim 8 , wherein the first control signal comprises a complementary input data signal.