Apparatus and method for clock synchronization for inter-die synchronized data transfer
Described is an apparatus for clock synchronization. The apparatus comprises a pair of interconnects; a first die including a first phase interpolator having an output coupled to one of the interconnects; and a second die, wherein the pair of interconnects is to couple the first die to the second die.
1. An apparatus comprising:
a clock generator;
an I/Q phase generator coupled to the clock generator;
a first phase interpolator coupled to a first output of the I/Q phase generator;
a phase detector having a first input coupled to an output of the first phase interpolator; and
a second phase interpolator coupled to a second output of the I/Q phase generator, wherein the first and second phase interpolators are on a first die, and wherein the phase detector has a second input which is to receive an input from a second die.
2. The apparatus of claim 1 , wherein the first output is to provide a first clock having a first phase, wherein the second output is to provide a second clock having a second phase, and wherein the first phase is to be separated from the second phase by 90 degrees.
3. The apparatus of claim 2 , wherein the second phase interpolator is communicatively coupled to a first interface which is to be coupled to a first circuit via a first interconnect.
4. The apparatus of claim 3 , wherein the second input is coupled to a second interface which is to be coupled to a second circuit via a second interconnect, wherein the first and second interconnects are coupled together at the second circuit.
5. The apparatus of claim 4 , wherein the second circuit is in the second die.
6. The apparatus of claim 1 comprises a delay estimator having a first input coupled to an output of the second phase interpolator, and a first output coupled to a first interface which is to be coupled to a first circuit via a first interconnect.
7. The apparatus of claim 6 , wherein the delay estimator comprises:
a divider;
a delay line coupled to an output of the divider;
a flip-flop coupled to the divider and the delay line; and
a buffer or inverter coupled to an output of the flip-flip.
8. The apparatus of claim 7 , wherein an output of the delay line is coupled to a clock input of the flip-flop, and wherein the output of the divider is coupled to a data input of the flip-flop.
9. The apparatus of claim 7 comprises a control logic which is to set a divider ratio of the divider.
10. The apparatus of claim 9 , wherein an output of the buffer or inverter is received by the control logic.
11. The apparatus of claim 1 , wherein the clock generator comprises a phase locked loop (PLL).