Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array
Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.
1. A memory array comprising:
a substrate;
a bitline comprising parallel bitline sections and a semiconductor region positioned laterally between the bitline sections, the bitline having a first surface adjacent to the substrate and comprising essentially co-planar bottom surfaces of the bitline sections and the semiconductor region and a second surface opposite the first surface and comprising essentially co-planar top surfaces of the bitline sections and the semiconductor region; and
a memory cell comprising a vertical field effect transistor,
the vertical field effect transistor comprising a first source/drain region,
the first source/drain region having a planar bottom surface immediately adjacent to the second surface such that the bitline is stacked between the substrate and the first source/drain region,
the first source/drain region having a first width,
the bitline having a second width that is equal to or less than the first width, and
the first source/drain region being essentially center-aligned above the bitline such that the first source/drain region completely traverses the bitline and such that the planar bottom surface of the first source/drain region is in direct contact with the co-planar top surfaces of the bitline sections and the semiconductor region.
2. The memory array of claim 1 ,
the first source/drain region comprising a first semiconductor material,
the bitline having a length,
the bitline sections comprising a pair of essentially parallel, elongated, bitline sections extending the length of the bitline and comprising a first bitline section and a second bitline section,
the semiconductor region being positioned laterally between the first bitline section and the second bitline section,
the semiconductor region and the first source/drain region being in discrete semiconductor layers, and
the semiconductor region comprising a second semiconductor material that is different from the first semiconductor material.
3. The memory array of claim 2 , the first semiconductor material comprising silicon and the second semiconductor material comprising silicon germanium.
4. The memory array of claim 1 , the vertical field effect transistor further comprising:
a channel region on the first source/drain region such that the first source/drain region is stacked between the bitline and the channel region, the channel region comprising any of a semiconductor fin and a semiconductor nanowire;
a second source/drain region on the channel region such that the channel region extends essentially vertically between the first source/drain region and the second source/drain region;
a gate laterally surrounding the channel region between the first source/drain region and the second source/drain region; and
spacer layers electrically isolating the gate from the first source/drain region and the second source/drain region.
5. The memory array of claim 4 , further comprising rows and columns of memory cells, the memory cells comprising vertical field effect transistors, respectively, wherein all the vertical field effect transistors of the memory cells in a given row have a shared gate for a wordline and wherein all the vertical field effect transistors of the memory cells in a given column have a shared bitline.
6. The memory array of claim 1 , further comprising interlayer dielectric material positioned laterally adjacent to the bitline and the first source/drain region, wherein an airgap is located between the bitline and the interlayer dielectric material.
7. A memory array comprising:
an isolation layer on a substrate;
a semiconductor layer on the isolation layer and comprising a first semiconductor material;
a bitline on the semiconductor layer and comprising parallel bitline sections and a semiconductor region positioned laterally between the bitline sections, the semiconductor region comprising a second semiconductor material that is different from the first semiconductor material and the bitline having a first surface immediately adjacent to the semiconductor layer and comprising essentially co-planar bottom surfaces of the bitline sections and the semiconductor region and a second surface opposite the first surface and comprising essentially co-planar top surfaces of the bitline sections and the semiconductor region; and
a memory cell comprising a vertical field effect transistor,
the vertical field effect transistor comprising a first source/drain region comprising the first semiconductor material,
the first source/drain region having a planar bottom surface immediately adjacent to the second surface such that the bitline is stacked between the substrate and the first source/drain region,
the first source/drain region having a first width,
the bitline having a second width that is less than the first width, and
the first source/drain region being essentially center-aligned above the bitline such that the first source/drain region completely traverses the bitline and such that the planar bottom surface of the first source/drain region is in direct contact with the co-planar top surfaces of the bitline sections and the semiconductor region.
8. The memory array of claim 7 ,
the bitline having a length,
the bitline sections comprising a pair of essentially parallel, elongated, bitline sections extending the length of the bitline and comprising a first bitline section and a second bitline section, and
the semiconductor region being positioned laterally between the first bitline section and the second bitline section.
9. The memory array of claim 7 , the bitline sections comprising metal, the first semiconductor material comprising silicon and the second semiconductor material.
10. The memory array of claim 7 , the vertical field effect transistor further comprising:
a channel region on the first source/drain region such that the first source/drain region is stacked between the bitline and the channel region, the channel region comprising any of a semiconductor fin and a semiconductor nanowire;
a second source/drain region on the channel region such that the channel region extends essentially vertically between the first source/drain region and the second source/drain region;
a gate laterally surrounding the channel region between the first source/drain region and the second source/drain region; and
spacer layers electrically isolating the gate from the first source/drain region and the second source/drain region.
11. The memory array of claim 10 , further comprising rows and columns of memory cells, the memory cells comprising vertical field effect transistors, respectively, wherein all the vertical field effect transistors of the memory cells in a given row have a shared gate for a wordline and wherein all the vertical field effect transistors of the memory cells in a given column have a shared bitline.
12. The memory array of claim 7 , further comprising interlayer dielectric material positioned laterally adjacent to the bitline and the first source/drain region, wherein an airgap is located either within the interlayer dielectric material or between the bitline and the interlayer dielectric material.
13. A memory array comprising:
an isolation layer on a substrate;
a silicon layer on the isolation layer;
a bitline on the silicon layer and comprising parallel bitline sections and a silicon germanium region positioned laterally between the bitline sections, the bitline having a first surface immediately adjacent to the silicon layer comprising essentially co-planar bottom surfaces of the bitline sections and the silicon germanium region and a second surface opposite the first surface and comprising essentially co-planar top surfaces of the bitline sections and the silicon germanium region; and
a memory cell comprising a vertical field effect transistor,
the vertical field effect transistor comprising a first source/drain region comprising silicon,
the first source/drain region having a planar bottom surface immediately adjacent to the second surface such that the bitline is stacked between the silicon layer and the first source/drain region,
the first source/drain region having a first width,
the bitline having a second width that is less than the first width, and
the first source/drain region being essentially center-aligned above the bitline such that the first source/drain region completely traverses the bitline and such that the planar bottom surface of the first source/drain region is in direct contact with the co-planar top surfaces of the bitline sections and the silicon germanium region.
14. The memory array of claim 13 ,
the bitline having a length,
the bitline sections comprising a pair of essentially parallel, elongated, bitline sections extending the length of the bitline and comprising a first bitline section and a second bitline section, and
the silicon germanium region being positioned laterally between the first bitline section and the second bitline section.
15. The memory array of claim 13 , the bitline sections comprising any of tungsten, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and nickel.
16. The memory array of claim 13 , the vertical field effect transistor further comprising:
a channel region on the first source/drain region such that the first source/drain region is stacked between the bitline and the channel region, the channel region comprising any of a silicon fin and a silicon nanowire;
a second source/drain region on the channel region such that the channel region extends essentially vertically between the first source/drain region and the second source/drain region;
a gate laterally surrounding the channel region between the first source/drain region and the second source/drain region; and
spacer layers electrically isolating the gate from the first source/drain region and the second source/drain region.
17. The memory array of claim 16 , further comprising rows and columns of memory cells, the memory cells comprising vertical field effect transistors, respectively, wherein all the vertical field effect transistors of the memory cells in a given row have a shared gate for a wordline and wherein all the vertical field effect transistors of the memory cells in a given column have a shared bitline.
18. The memory array of claim 13 , further comprising interlayer dielectric material positioned laterally adjacent to the bitline and the first source/drain region, wherein an airgap is located either within the interlayer dielectric material or between the bitline and the interlayer dielectric material.