2-D material transistor with vertical structure
Semiconductor structures including two-dimensional ( 2 -D) materials and methods of manufacture thereof are described. By implementing 2 -D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2 -D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.
1. A semiconductor structure comprising:
a substrate comprising first and second fins, wherein the first and second fins are separated by an inner gate electrode region;
a first gate stack comprising a first two dimensional (2-D) material layer extending continuously from a first sidewall of the first fin to a first sidewall of the second fin and a first outer gate insulator layer on the first 2-D material layer having a length shorter than that of the first 2-D material layer; and
a second gate stack comprising a second 2-D material layer extending continuously from a second sidewall of the first fin to a second sidewall of the second fin and a second outer gate insulator layer on the second 2-D material layer having a length shorter than that of the second 2-D material layer.
2. The semiconductor structure of claim 1 , wherein the first gate stack further comprises:
a first inner gate insulator layer formed between the first 2-D material layer and the inner gate electrode region; and
a first gate electrode region formed on the first outer gate insulator layer.
3. The semiconductor structure of claim 2 , wherein the second gate stack further comprises:
a second inner gate insulator layer formed between the second 2-D material layer and the inner gate electrode region; and
a second gate electrode region formed on the second outer gate insulator layer.
4. The semiconductor structure of claim 3 , wherein the inner gate electrode region and the first and second gate electrode regions are in electrical contact.
5. The semiconductor structure of claim 1 , further comprising:
a first terminal in electrical contact with the first and second 2-D material layers and the first fin.
6. The semiconductor structure of claim 5 , further comprising:
a second terminal in electrical contact with the first and second 2-D material layers and the second fin.
7. The semiconductor structure of claim 1 , wherein the 2-D material layer comprises graphene.
8. The semiconductor structure of claim 1 , wherein the 2-D material layer comprises a transition metal dichalcogenide (TMD) material.
9. The semiconductor structure of claim 1 , wherein the 2-D material layer comprises phosphorene.
10. The semiconductor structure of claim 1 , wherein the first 2-D material layer is formed on the first sidewalls of the first and second fins.
11. The semiconductor structure of claim 1 , wherein the second 2-D material layer is formed on the second sidewalls of the first and second fins.
12. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate comprising a fin, wherein the fin comprises first and second sidewalls;
depositing respective first and second two-dimensional (2-D) material layers on the first and second sidewalls;
depositing a first gate insulator layer and a first gate electrode over the first and second 2-D material layers;
etching a recess in the fin between the first and second 2-D material layers;
forming a second gate insulator layer and a second gate electrode layer in the recess between the first and second 2-D material layers; and
patterning the first gate insulator layer and the first gate electrode to form a gate stack having a length shorter than that of the first and second 2-D material layers.
13. The method of claim 12 , wherein the second gate insulator layer is formed directly over the first and second 2-D material layers.
14. The method of claim 12 , wherein the first and second gate electrodes are electrically coupled.
15. The method of claim 12 , wherein the first and second 2-D material layers comprise graphene.
16. The method of claim 12 , wherein the first and second 2-D material layers comprise a transition metal dichalcogenide (TMD) material.
17. The method of claim 12 , wherein the first and second 2-D material layers comprise phosphorene.
18. A semiconductor structure comprising;
a substrate comprising a fin, wherein the fin comprises opposing sidewalls and a top surface;
a two-dimensional (2-D) material layer over the opposing sidewalls and the top surface of the fin;
a first dielectric layer over the 2-D material layer;
a second dielectric layer between the fin and the 2-D material;
a gate electrode over a portion of the first dielectric layer; and
source and drain terminals over the 2-D material layer, wherein the source and drain terminals are on opposing sides of the gate electrode.
19. The semiconductor structure of claim 18 , wherein the 2-D material layer comprises graphene, transition metal dichalcogenide (TMD) material, or phosphorene.
20. The semiconductor structure of claim 2 , wherein the first inner gate insulator layer has a length equal to or shorter than the length of the first outer gate insulator layer.
21. The semiconductor structure of claim 3 , wherein the second inner gate insulator layer has a length equal to or shorter than the length of the second outer gate insulator layer.