Method for compensation of manufacturing tolerances of at least one electric parameter of a power transistor and associated system
The system ( 21 ) includes: a power transistor ( 22 ), a data medium ( 60 ) including data relating to the manufacturing tolerance (Tol) of at least one electric parameter of the transistor ( 22 ), an electric circuit ( 26 ) for controlling the transistor adapted so as to operate for a reference value of the parameter (V REF ), an electric circuit ( 64 ) having an inductance of less than 100 nH and such that the assembly ( 70 ) formed with the circuit ( 64 ) and the transistor ( 22 ) has a value for the parameter, for which the deviation in absolute with the reference value is strictly less than the manufacturing tolerance (Tol).
1. A system comprising:
an assembly including an electric circuit and a transistor,
wherein the assembly is configured to receive data including a reference parameter of the transistor and a manufacturing tolerance of the reference parameter,
wherein the assembly is characterized by an electric parameter;
wherein an inductance of the electric circuit is selected such that an absolute value of a difference between the electric parameter and the reference parameter is strictly less than the manufacturing tolerance; and
wherein the reference parameter is one selected from the group consisting of a switching characteristic of the transistor, a Miller capacitance of the transistor, a delay time of the transistor, and a rise time of the transistor.
2. The system of claim 1 , wherein the inductance is less than 100 nH.
3. The system of claim 1 , wherein the inductance is less than 75 nH.
4. The system of claim 1 , further including a control circuit configured to drive the transistor.
5. The system of claim 4 , wherein the control circuit includes an optical receiver.
6. The system of claim 1 , wherein the transistor is an insulated gate bipolar transistor (IGBT).
7. The system of claim 6 , wherein the IGBT has a diode disposed between two conducting terminals.
8. The system of claim 1 , wherein further including another assembly similarly configured to the assembly.
9. The system of claim 8 , wherein the system is configured to simultaneously trigger the assembly and the other assembly.
10. The system of claim 1 , wherein the transistor is a power transistor.