Phase detection method based on a plurality of consecutive values of a receiving signal

1. A phase detection method comprising the following steps:

receiving a plurality of consecutive values of a receiving signal (Y) with a known sampling frequency f s as a reaction to a transmitting signal with a known transmitting frequency f w ;

determining two differential values (ΔY 1 , ΔY 2 ), each coming from two consecutive values out of three consecutive values (Y 1 , Y 2 , Y 3 ) of the receiving signal (Y); and

determining a phase real part (U) and a phase imaginary part (V) of the receiving signal (Y) based on a linear relation between the phase real part (U), the phase imaginary part (V) and the two differential values (ΔY 1 , ΔY 2 ).

2. The phase detection method according to claim 1 , wherein the linear relation between the phase real part (U), the phase imaginary part (V) and the two differential values (ΔY 1 , ΔY 2 ) can be represented by a two-dimensional linear system of equations based on the two differential values (ΔY 1 , ΔY 2 ) as input variables and the phase real part (U) and the phase imaginary part (V) as output variables.

3. The phase detection method according to claim 2 , wherein the linear system of equations is solved by weighting of the input variables with Fourier Coefficients based on a known circular frequency Ω, wherein said known circular frequency Ω depends on the transmitting frequency f w and the sampling frequency f s .

4. The phase detection method according to claim 3 , wherein the known circular frequency Ω satisfies the following condition: Ω=2π(f w /f s ).

5. The phase detection method according to claim 3 including determining the Fourier Coefficients in dependence of the known circular frequency Ω before determining the phase real part (U) and the phase imaginary part (V) of the receiving signal (Y).

6. The phase detection method according to claim 1 including determining a bias (β) of the receiving signal (Y) based on a linear relation between the phase real part (U), the phase imaginary part (V), the bias (β), and the three consecutive values (Y 1 , Y 2 , Y 3 ) of the receiving signal (Y).

7. A processor for determining a phase of a receiving signal (Y) received as a reaction to a transmitting signal with a known transmitting frequency f w , said receiving signal (Y) having a known sampling frequency f s , said processor comprising:

a first input register, a second input register, and a third input register, each input register being configured for storing one of three consecutive values (Y 1 , Y 2 , Y 3 ) from a plurality of consecutive values of the receiving signal (Y) one after the other;

a first internal register and a second internal register, each of which being configured for storing either a first differential value (ΔY 1 ) as a difference of the content (Y 2 ) of the second input register and the content (Y 1 ) of the first input register or a second differential value (ΔY 2 ) as a difference of the content (Y 3 ) of the third input register and the content (Y 2 ) of the second input register;

a first output register and a second output register, each of which being configured for providing either a phase real part (U) or a phase imaginary part (V) of the receiving signal (Y); and

a computing unit configured for determining the phase real part (U) and the phase imaginary part (V) of the receiving signal (Y) based on a linear relation between the phase real part (U), the phase imaginary part (V), and the two differential values (ΔY 1 , ΔY 2 ).

8. The processor according to claim 7 including a third output register configured for providing a bias (β) of the receiving signal (Y), wherein the computing unit is configured for determining the bias (β) of the receiving signal (Y) based on a linear relation between the phase real part (U), the phase imaginary part (V), the bias (β), and the three consecutive values (Y 1 , Y 2 , Y 3 ) of the receiving signal (Y).

9. The processor according to claim 8 including a first coefficient register, a second coefficient register, a third coefficient register, and a fourth coefficient register, each of which being configured for storing Fourier Coefficients, wherein said Fourier Coefficients determine a linear relation between the phase real part (U), the phase imaginary part (V), and the two differential values (ΔY 1 , ΔY 2 ).

10. The processor according to claim 9 including a first parameter memory, a second parameter memory, a third parameter memory, and a fourth parameter memory, said first parameter memory being configured for storing a cosine (hC) of a half of a known circular frequency Ω, which depends on the transmitting frequency f w and the sampling frequency f s , said second parameter memory being configured for storing a sine (hS) of the half of the known circular frequency Ω, said third parameter memory being configured for storing a cosine (wC) of the known circular frequency Ω, and said fourth parameter memory being configured for storing a sine (wS) of the known circular frequency Ω.

11. The processor according to claim 10 , wherein the known circular frequency Ω satisfies the following condition: Ω=2π(f w /f s ).

12. The processor according to claim 10 , wherein the computing unit is configured for determining the phase real part (U) and the phase imaginary part (V) of the receiving signal (Y) based on the contents (C 1 , S 1 , C 2 , S 2 ) of the four coefficient registers and the contents (hC, hS, wC, wS) of the four parameter memories.

13. The processor according to claim 12 including an instruction unit configured for initializing the first coefficient register with the content (hC) of the first parameter memory and for initializing the second coefficient register with the content (hS) of the second parameter memory in response to a reset signal, and for renewing the first coefficient register with the content (C 2 ) of the third coefficient register and for renewing the second coefficient register with the content (S 2 ) of the fourth coefficient register in response to a clock signal, wherein the instruction unit is configured for loading the fourth coefficient register with the value C 1 wS+S 1 wC and for loading the third coefficient register with the value C 1 wC−S 1 wS in response to the clock signal, wherein wS denotes the content of the fourth parameter memory, wC denotes the content of the third parameter memory, C 1 denotes the content of the first coefficient register, S 1 denotes the content of the second coefficient register, and Ω denotes the known circular frequency Ω=2π(f w /f s ), wherein the computing unit is configured for determining the phase real part (U) as

Δ

⁢

⁢

Y

1

·

S

2

-

Δ

⁢

⁢

Y

2

·

S

1

4

⁢

hS

·

hS

·

hC

and the phase imaginary part (V) as

Δ

⁢

⁢

Y

1

·

C

2

-

Δ

⁢

⁢

Y

2

·

C

1

4

⁢

hS

·

hS

·

hC

,

wherein hS denotes the content of the second parameter memory, hC denotes the content of the first parameter memory, C 2 denotes the content of the third coefficient register, S 2 denotes the content of the fourth coefficient register, and Ω denotes the known circular frequency Ω=2π(f w /f w ).

14. The processor according to claim 13 , wherein the computing unit is configured for determining the bias (β) as Y 2 −(U·(S 1 hC+C 1 hS)+V·(C 1 hC−S 1 hS)), wherein U denotes the phase real part, V denotes the phase imaginary part, and Y 2 denotes the content of the second input register.

15. The processor according to claim 12 including a first auxiliary register, a second auxiliary register, and a counter incremented at every renewal of the three input registers depending on the clock signal, wherein the computing unit is configured for determining the phase real part (U) as ΔY 1 S 2 −ΔY 2 S 1 and the phase imaginary part (V) as ΔY 1 C 2 −ΔY 2 C 1 , for adding the phase real part (U) to the first auxiliary register and for adding the phase imaginary part (V) to the second auxiliary register, wherein the instruction unit is configured for outputting the values (AU, AV) of the two auxiliary registers divided by the value 2·wS·hS=4hS·hS·hC and divided by a value (cnt) of the counter in response to an interruption signal, wherein ΔY 1 denotes the content of the first internal register, ΔY 2 denotes the content of the second internal register, C 2 denotes the content of the third coefficient register, S 2 denotes the content of the fourth coefficient register, hS denotes the content of the second parameter memory and hC denotes the content of the first parameter memory, and Ω denotes the known circular frequency Ω=2π(f w /f s ).