IP Library › Granted Patent US 10,140,123
Granted Patent B2
US 10,140,123 · App. 15/483,745 · Granted Nov 27, 2018

SIMD processing lanes storing input pixel operand data in local register file for thread execution of image processing operations

Inventors: Michael J. Mantor (Orlando, FL); Brian Emberling (Sunnyvale, CA)
Assignee: ADVANCED MICRO DEVICES, INC.
G06F9/3009G06F9/30098G06F9/3851G06F9/3887G06F15/8007
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,140,123
App. No.
15/483,745
Granted
Nov 27, 2018
Kind
B2
Abstract

A graphics processing unit is disclosed, the graphics processing unit having a processor having one or more SIMD processing units, and a local data share corresponding to one of the one or more SIMD processing units, the local data share comprising one or more low latency accessible memory regions for each group of threads assigned to one or more execution wavefronts, and a global data share comprising one or more low latency memory regions for each group of threads.

Claims (42)

1. A non-transitory computer-readable medium having stored thereon computer-executable instructions that, if executed by a computing device, cause the computing device to perform a method comprising:

allocating a set of pixels of an image to a set of single-instruction multiple-data (SIMD) processors;

allocating a subset of pixels of the set of pixels to each thread executing on a processing lane of each of the set of SIMD processors;

storing the subset of pixels in a general purpose register (GPR) file associated with each processing lane;

computing a per-thread private result based on the subset of pixels in a private space in the GPR file;

accumulating the per-thread private result with additional per-thread private results computed by threads from a same lane to generate a per-lane local result stored in a global space in the GPR file; and

writing the per-lane local result from the global space in the GPR file to a private area of a local data share (LDS) associated with the processing lane, the LDS associated only with a SIMD processor of the set of SIMD processors which contains the processing lane.

2. The non-transitory computer-readable medium of claim 1 , the method further comprising:

reading each per-lane local result from the LDS into a first single GPR file of a first single processing lane;

reducing the results of all per-lane local results from the LDS to find a SIMD-local result; and

writing the SIMD-local result from the first single GPR file to a private area of a global data share (GDS) associated with the first single processing lane.

3. The non-transitory computer-readable medium of claim 2 , the method further comprising:

reading each SIMD-local result from the GDS into a second single GPR file of a second single processing lane;

reducing the results of all SIMD-local results from the GDS to find a final result; and

writing the final result.

4. The non-transitory computer-readable medium of claim 3 , wherein writing the final result comprises:

writing the final result to a memory location.

5. The non-transitory computer-readable medium of claim 3 , wherein writing the final result comprises writing the final result back to the GDS, the method further comprising:

executing a broadcast read instruction;

populating the GPR with the final result from the GDS responsive to the broadcast read instruction; and

computing a subsequent per-thread private result using the final result as an intermediate result in a subsequent computation.

6. A method comprising:

allocating a set of pixels of an image to a set of single-instruction multiple-data (SIMD) processors;

allocating a subset of pixels of the set of pixels to each thread executing on a processing lane of each of the set of SIMD processors;

storing the subset of pixels in a general purpose register (GPR) file associated with each processing lane;

computing a per-thread private result based on the subset of pixels in a private space in the GPR file;

accumulating the per-thread private result with additional per-thread private results computed by threads from a same lane to generate a per-lane local result stored in a global space in the GPR file; and

writing the per-lane local result from the global space in the GPR file to a private area of a local data share (LDS) associated with the processing lane, the LDS associated only with a SIMD processor of the set of SIMD processors which contains the processing lane.

7. The method of claim 6 further comprising:

reading each per-lane local result from the LDS into a first single GPR file of a first single processing lane;

reducing the results of all per-lane local results from the LDS to find a SIMD-local result; and

writing the SIMD-local result from the first single GPR file to a private area of a global data share (GDS) associated with the first single processing lane.

8. The method of claim 7 further comprising:

reading each SIMD-local result from the GDS into a second single GPR file of a second single processing lane;

reducing the results of all SIMD-local results from the GDS to find a final result; and

writing the final result.

9. The method of claim 8 , wherein writing the final result comprises:

writing the final result to a memory location.

10. The method of claim 8 , wherein writing the final result comprises writing the final result back to the GDS, the method further comprising:

executing a broadcast read instruction;

populating the GPR with the final result from the GDS responsive to the broadcast read instruction; and

computing a subsequent per-thread private result using the final result as an intermediate result in a subsequent computation.

Continuity (3)
Division 12476130 · Jun 1, 2009
Provisional Application 61057534 · May 30, 2008
Related Publication 20170212757A1 · Jul 27, 2017